MT48LC2M32B2TG-7ITG Datasheet, PDF (39/80 Pages) Micron Technology – SDR SDRAM MT48LC2M32B2 – 512K x 32 x 4 Banks

Figure 13: Mode Register Definition
64Mb: x32 SDRAM
Mode Register
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
12 11 10 9 8 7
Reserved
WB Op Mode
6 5 43
CAS Latency BT
2 10
Burst Length
Mode Register (Mx)
Program
BA1, BA0 = “0, 0”
to ensure compatibility
with future devices.
M9
Write Burst Mode
0
Programmed Burst Length
1
Single Location Access
M8
M7
M6-M0
Operating Mode
0
0
Defined Standard Operation
–
–
–
All other states reserved
M2 M1 M0
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
Burst Length
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
M3
Burst Type
0
Sequential
1
Interleaved
M6 M5 M4
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
CAS Latency
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
PDF: 09005aef811ce1fe
64mb_x32_sdram.pdf - Rev. T 04/13 EN
39
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