MT48H8M16LF Datasheet, PDF (60/64 Pages) Micron Technology – Synchronous DRAM

128Mb: x16 Mobile SDRAM
Timing Diagrams
Figure 46: Single WRITE – With Auto Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP3
NOP3
NOP3
WRITE
NOP
NOP
DQMU, DQML
tCMS tCMH
A0-A9, A11
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
ROW
tAS tAH
BANK
COLUMN m ²
ENABLE AUTO PRECHARGE
BANK
NOP
ACTIVE
NOP
ROW
ROW
BANK
DQ
tRCD
tRAS
tRC
tDS tDH
DIN m
tWR
tRP
DON’T CARE
Notes: 1. For this example, BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.
3. A9 and A11 are “Don’t Care.”
4. WRITE command not allowed or ^tRAS would be violated.
PDF: 09005aef80c97087/Source: 09005aef80c97015
MT48H8M16_2.fm - Rev. E 3/05 EN
60
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