MT48H8M16LF Datasheet, PDF (20/64 Pages) Micron Technology – Synchronous DRAM

128Mb: x16 Mobile SDRAM
READs
last desired data element of a longer burst that is being truncated. The new READ com-
mand should be issued x cycles before the clock edge at which the last desired data ele-
ment is valid, where x equals the CAS latency minus one.
This is shown in Figure 10, "Consecutive READ Bursts," on page 21 for CAS latencies of
two and three; data element n + 3 is either the last of a burst of four or the last desired of
a longer burst. The 128Mb SDRAM uses a pipelined architecture and therefore does not
require the 2n rule associated with a prefetch architecture. A READ command can be ini-
tiated on any clock cycle following a previous READ command. Full-speed random read
accesses can be performed to the same bank, as shown in Figure 11, "Random READ
Accesses," on page 22, or each subsequent READ may be performed to a different bank.
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst may be ini-
tiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQ go High-Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
Figure 9: READ Command
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
A0-A8
A9, A11
A10
BA0,1
COLUMN
ADDRESS
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK
ADDRESS
DON’T CARE
PDF: 09005aef80c97087/Source: 09005aef80c97015
MT48H8M16_2.fm - Rev. E 3/05 EN
20
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