MT48H8M16LF Datasheet, PDF (34/64 Pages) Micron Technology – Synchronous DRAM

128Mb: x16 Mobile SDRAM
Power-Down
Table 7: Truth Table 2 – CKE
Notes: 1-4; Notes appear below table.
CKE_n-1 CKE_n
L
L
L
H
H
L
H
H
Current State
Power-Down
Self Refresh
Clock Suspend
Deep Power-Down
Power-Down
Deep Power-Down
Self Refresh
Clock Suspend
All Banks Idle
All Banks Idle
All Banks Idle
Reading or Writing
Command_n
X
X
X
X
COMMAND INHIBIT or NOP
X
COMMAND INHIBIT or NOP
X
COMMAND INHIBIT or NOP
BURST TERMINATE
AUTO REFRESH
VALID
See Truth Table 3
Action_n
Maintain Power-Down
Maintain Self Refresh
Maintain Clock Suspend
Maintain Deep Power-Down
Exit Power-Down
Exit Deep Power-Down
Exit Self Refresh
Exit Clock Suspend
Power-Down Entry
Deep Power-Down Entry
Self Refresh Entry
Clock Suspend Entry
Notes
8
5
8
6
7
8
Notes: 1. CKE_n is the logic state of CKE at clock edge n; CKE_n-1 was the state of CKE at the previous
clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMAND_n is the command registered at clock edge n, and ACTION_n is a result of COM-
MAND_n.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time
for clock edge n + 1 (provided that ^tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once ^tXSR
is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occur-
ring during the ^tXSR period. A minimum of two NOP commands must be provided during
t_{XSR period.}
7. After exiting clock suspend at clock edge n, the device will resume operation and recog-
nize the next command at clock edge n + 1.
8. Deep power-down is a power-saving feature of this Mobile SDRAM device. This command
is BURST TERMINATE when CKE is HIGH and DEEP POWER-DOWN when CKE is LOW.
PDF: 09005aef80c97087/Source: 09005aef80c97015
MT48H8M16_2.fm - Rev. E 3/05 EN
34
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