MT48LC8M16LFFF Datasheet, PDF (58/61 Pages) Micron Technology – SYNCHRONOUS DRAM

ADVANCE
128Mb: x16, x32
MOBILE SDRAM
WRITE – DQM OPERATION¹
T0
T1
T2
T3
CLK
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
DQMU, DQML
A0-A9, A11
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
ROW
tAS tAH
BANK
DQ
NOP
WRITE
NOP
tCMS tCMH
COLUMN m ²
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK
tDS tDH
DIN m
tRCD
T4
T5
T6
NOP
NOP
NOP
tDS tDH
DIN m + 2
tDS tDH
DIN m + 3
T7
NOP
DON’T CARE
TIMING PARAMETERS
SYMBOL*
t_AH
t_AS
t_CH
t_CL
t_{CK (3)}
t_{CK (2)}
t_{CK (1)}
-8
MIN MAX
1
2.5
3
3
8
10
20
-10
MIN MAX
1
2.5
3
3
10
12
25
UNITS
ns
ns
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. x16: A9 and A11 = “Don’t Care”
x32: A8, A9,and A11 = “Don’t Care”
SYMBOL*
t_CKH
t_CKS
t_CMH
t_CMS
t_DH
t_DS
t_RCD
-8
MIN MAX
1
2.5
1
2.5
1
2.5
20
-10
MIN MAX
1
2.5
1
2.5
1
2.5
20
UNITS
ns
ns
ns
ns
ns
ns
ns
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
58
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©2002, Micron Technology, Inc.