MT48LC8M16LFFF Datasheet, PDF (47/61 Pages) Micron Technology – SYNCHRONOUS DRAM

ADVANCE
128Mb: x16, x32
MOBILE SDRAM
SINGLE READ – WITHOUT AUTO PRECHARGE¹
T0
CLK
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
DQMU, DQML
A0-A9, A11
tAS tAH
ROW
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
BANK
T1
T2
T3
tCK
tCL
tCH
NOP
READ
tCMS tCMH
NOP ³
COLUMN m²
DISABLE AUTO PRECHARGE
BANK
T4
T5
T6
NOP ³
PRECHARGE
NOP
ALL BANKS
SINGLE BANKS
BANK(S)
T7
ACTIVE
ROW
ROW
BANK
T8
NOP
DQ
tRCD
tRAS
tRC
tAC
tOH
tLZ
DOUT m
tHZ
CAS Latency
tRP
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL*
t_{AC (3)}
t_{AC (2)}
t_{AC (1)}
t_AH
t_AS
t_CH
t_CL
t_{CK (3)}
t_{CK (2)}
t_{CK (1)}
t_CKH
t_CKS
-8
MIN MAX
7
8
19
1
2.5
3
3
8
10
20
1
2.5
-10
MIN MAX
7
8
22
1
2.5
3
3
10
12
25
1
2.5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL*
t_CMH
t_CMS
t_{HZ (3)}
t_{HZ (2)}
t_{HZ (1)}
t_LZ
t_OH
t_RAS
t_RC
t_RCD
t_RP
-8
MIN MAX
1
2.5
7
8
19
1
2.5
48 120,000
80
20
20
-10
MIN MAX UNITS
1
ns
2.5
ns
7
ns
8
ns
22
ns
1
ns
2.5
ns
50 120,000 ns
100
ns
20
ns
20
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a “manual”
PRECHARGE.
2. x16: A9 and A11 = “Don’t Care”
x32: A8, A9,and A11 = “Don’t Care”
3. PRECHARGE command not allowed or ^tRAS would be violated.
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
47
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.