MT48LC8M16LFFF Datasheet, PDF (41/61 Pages) Micron Technology – SYNCHRONOUS DRAM

ADVANCE
128Mb: x16, x32
MOBILE SDRAM
POWER-DOWN MODE¹
T0
CLK
T1
tCK
T2
tCL
((
))
tCH
tCKS
((
))
CKE
((
tCKS tCKH
))
tCMS tCMH
((
COMMAND PRECHARGE
NOP
NOP
))
((
))
((
))
DQML, DQMU
((
))
((
A0-A9, A11
))
((
))
ALL BANKS
((
A10
))
((
SINGLE BANK
))
tAS tAH
((
BA0, BA1
BANK(S)
))
((
))
High-Z
DQ
Precharge all
active banks
Two clock cycles
All banks idle, enter
power-down mode
((
))
Input buffers gated off while in
power-down mode
Exit power-down mode
Tn + 1
tCKS
Tn + 2
NOP
ACTIVE
ROW
ROW
BANK
All banks idle
DON’T CARE
TIMING PARAMETERS
SYMBOL*
t_AH
t_AS
t_CH
t_CL
t_{CK (3)}
t_{CK (2)}
-8
MIN MAX
1
2.5
3
3
8
10
-10
MIN MAX
1
2.5
3
3
10
12
UNITS
ns
ns
ns
ns
ns
ns
SYMBOL*
t_{CK (1)}
t_CKH
t_CKS
t_CMH
t_CMS
*CAS latency indicated in parentheses.
NOTE: 1. Violating refresh requirements during power-down may result in a loss of data.
-8
MIN MAX
20
1
2.5
1
2.5
-10
MIN MAX
25
1
2.5
1
2.5
UNITS
ns
ns
ns
ns
ns
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
41
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©2002, Micron Technology, Inc.