MT48LC8M16LFFF Datasheet, PDF (1/61 Pages) Micron Technology – SYNCHRONOUS DRAM

SYNCHRONOUS
DRAM
ADVANCE^‡
128Mb: x16, x32
MOBILE SDRAM
MT48LC8M16LFFF, MT48V8M16LFFF – 2 Meg x 16 x 4 banks
MT48LC4M32LFFC , MT48V4M32LFFC – 1 Meg x 32 x 4 banks
For the latest data sheet revisions, please refer to the Micron Web
site: www.micron.com/dramds
FEATURES
• Temperature Compensated Self Refresh (TCSR)
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode; standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Low voltage power supply
• Partial Array Self Refresh power-saving mode
• Operating Temperature Range
Industrial (-40^oC to +85^oC)
OPTIONS
MARKING
• VDD/VDDQ
3.3V/3.3V
2.5V/2.5V or 1.8V
• Configurations
8 Meg x 16 (2 Meg x 16 x 4 banks)
4 Meg x 32 (1 Meg x 32 x 4 banks)
LC
V
8M16
4M32
• Package/Ball out
Plastic Package
54-ball FBGA (8mm x 9mm)(x16 only)
FF¹
90-ball FBGA (11mm x 13mm)
FC¹
• Timing (Cycle Time)
8ns @ CL = 3 (125 MHz)
-8
10ns @ CL = 3 (100 MHz)
-10
Part Number Example:
MT48V8M16LFFC-8
NOTE: 1. See page 61 for FBGA/VFBGA Device Marking
Table.
PIN ASSIGNMENT (Top View)
54-Ball VFBGA
1
2
3
4
5
6
7
8
9
A
VSS
DQ15 VSSQ
VDDQ DQ0
VDD
B
DQ14 DQ13 VDDQ
VSSQ
DQ2
DQ1
C
DQ12 DQ11 VSSQ
VDDQ DQ4
DQ3
D
DQ10 DQ9 VDDQ
VSSQ
DQ6
DQ5
E
DQ8
NC
VSS
VDD LDQM _DQ7
F
UDQM CLK
CKE
CAS# RAS#
WE#
G NC/A12 A11
A9
BA0
BA1
CS#
H
A8
A7
A6
A0
A1
A10
J
VSS
A5
A4
Top View
(Ball Down)
A3
A2
VDD
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
8 Meg x 16
4 Meg x 32
2 Meg x 16 x 4 banks 1 Meg x 32 x 4 banks
4K
4K
4K (A0–A11)
4K (A0–A11)
4 (BA0, BA1)
4 (BA0, BA1)
512 (A0–A8)
256 (A0–A7)
KEY TIMING PARAMETERS
SPEED CLOCK
ACCESS TIME
GRADE FREQUENCY CL=1* CL=2* CL=3*
-8
125 MHz
–
–
7ns
-10
100 MHz
–
–
7ns
-8
100 MHz
–
8ns
–
-10
83 MHz
–
8ns
–
-8
50 MHz 19ns –
–
-10
40 MHz 22ns –
–
t_RCD
20ns
20ns
20ns
20ns
20ns
20ns
t_RP
20ns
20ns
20ns
20ns
20ns
20ns
*CL = CAS (READ) latency
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
‡_{PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PUROPOSES ONLY AND ARE SUBJECT TO CHANGE BY}
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION AND DATA SHEET SPECIFICATIONS.