MT48V16M16LFFG Datasheet, PDF (52/58 Pages) Micron Technology – MOBILE SDRAM

ADVANCE
256Mb: x16
MOBILE SDRAM
SINGLE WRITE – WITHOUT AUTO PRECHARGE ¹
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP ²
NOP ²
PRECHARGE
NOP
ACTIVE
NOP
DQM /
DQML, DQMU
A0-A9, A11
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
ROW
tAS tAH
BANK
tCMS tCMH
COLUMN m ³
DISABLE AUTO PRECHARGE
BANK
ALL BANKS
SINGLE BANK
BANK
ROW
BANK
tDS tDH
DQ
DIN m
tRCD
t _WR 4
tRP
tRAS
tRC
DON’T CARE
NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. PRECHARGE command not allowed else ^tRAS would be violated.
3. x16: A9, A11 and A12 = “Don’t Care”
4. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency. With a single write
t_{WR has been increased to meet minimum} t_{RAS requirement.}
TIMING PARAMETERS
SYMBOL*
t_AH
t_AS
t_CH
t_CL
t_{CK (3)}
t_{CK (2)}
t_{CK (1)}
t_CKH
t_CKS
-8
MIN MAX
1
2.5
3
3
8
10
20
1
2.5
-10
MIN MAX
1
2.5
3
3
10
12
25
1
2.5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
SYMBOL*
t_CMH
t_CMS
t_DH
t_DS
t_RAS
t_RC
t_RCD
t_RP
t_WR
-8
MIN MAX
1
2.5
1
2.5
48 120,000
80
20
20
15
-10
MIN MAX UNITS
1
ns
2.5
ns
1
ns
2.5
ns
50 120,000 ns
100
ns
20
ns
20
ns
15
ns
256Mb: x16 Mobile SDRAM
MobileRamY26L_A.p65 – Pub. 5/02
52
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©2002, Micron Technology, Inc.