MT48V16M16LFFG Datasheet, PDF (1/58 Pages) Micron Technology – MOBILE SDRAM

MOBILE SDRAM
ADVANCE^‡
256Mb: x16
MOBILE SDRAM
MT48V16M16LFFG, MT48H16M16LFFG–
4 Meg x 16 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/dramds
FEATURES
• Temperature Compensated Self Refresh (TCSR)
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Low voltage power supply
• Deep Power Down
• Partial Array Self Refresh power-saving mode
• Industrial operating temperature (-40^oC to +85^oC)
OPTIONS
• VDD/VDDQ
2.5V/1.8V
1.8V/1.8V
• Configurations
16 Meg x 16 (4 Meg x 16 x 4 banks)
• WRITE Recovery (^tWR/^tDPL)
t_{WR = 2 CLK}
• Plastic Packages – OCPL¹
54-ball FBGA (8mm x 14mm)
• Timing (Cycle Time)
8.0ns @ CL = 3 (125MHz)
10ns @ CL = 3 (100MHz)
MARKING
V
H
16M16
FG¹
-8
-10
NOTE: 1. See page 58 for FBGA Device Marking Table.
256Mb SDRAM PART NUMBERS
PART NUMBER
MT48V16M16LFFG
MT48H16M16LFFG
ARCHITECTURE
16 Meg x 16
16 Meg x 16
VDD
2.5V
1.8V
PIN ASSIGNMENT (Top View)
54-Ball FBGA
1
2
3
4
5
6
7
8
9
A VSS DQ15 VSSQ
VDDQ DQ0 _VDD
B DQ14 DQ13 VDDQ
VSSQ DQ2 _DQ1
C DQ12 DQ11 VSSQ
VDDQ DQ4 _DQ3
D DQ10 DQ9 VDDQ
VSSQ DQ6 _DQ5
E DQ8 NC VSS
VDD LDQM _DQ7
F UDQM CK CKE
CAS\ RAS\ _WE\
G NC/A12 A11 A9
BA0 BA1 _CS\
H A8 A7 A6
A0 A1 _A10
J VSS A5 A4
A3 A2 _VDD
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
16 Meg x 16
4 Meg x 16 x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
512 (A0–A8)
KEY TIMING PARAMETERS
SPEED
GRADE
-8
-10
-8
-10
-8
-10
CLOCK
FREQUENCY
125 MHz
100 MHz
100 MHz
83 MHz
50 MHz
40 MHz
ACCESS TIME
CL=1* CL=2* CL=3*
–
–
7ns
–
–
7ns
–
8ns
–
–
8ns
–
19ns –
–
22ns –
–
SETUP HOLD
TIME TIME
2.5ns 1.0ns
2.5ns 1.0ns
2.5ns 1.0ns
2.5ns 1.0ns
2.5ns 1.0ns
2.5ns 1.0ns
*CL = CAS (READ) latency
256Mb: x16 Mobile SDRAM
MobileRamY26L_A.p65 – Pub. 5/02
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
‡_{PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PUROPOSES ONLY AND ARE SUBJECT TO CHANGE BY}
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION AND DATA SHEET SPECIFICATIONS.