MT48LC64M4A2_03 Datasheet, PDF (50/61 Pages) Micron Technology – SYNCHRONOUS DRAM 256Mb: x4, x8, x16 SDRAM

256Mb: x4, x8, x16
SDRAM
Figure 44: Read – Full-Page Burst¹
T0
T1
T2
T3
CLK
tCL
tCK
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
DQM/
DQML, DQMU
tCMS tCMH
A0-A9, A11, A12
tAS tAH
ROW
COLUMN m²
tAS tAH
A10
ROW
BA0, BA1
tAS tAH
BANK
BANK
DQ
tRCD
tAC
tLZ
CAS Latency
T4
NOP
T5
NOP
T6
( ( ^{Tn + 1}
))
((
))
((
))
((
))
((
))
NOP _{( (}
))
((
))
((
))
NOP
Tn + 2
Tn + 3
BURST TERM
NOP
Tn + 4
NOP
((
))
((
))
((
))
((
))
((
))
((
))
tAC
tOH
DOUT m
tAC
tOH
DOUT m+1
tAC _{( (}
tOH ^{) )}
((
))
DOUT m+2_{( (}
))
tAC
tOH
DOUT m-1
512 (x16) locations within same row
1,024 (x8) locations within same row
2,048 (x4) locations within same row
tAC
tOH
Dout m
Full page completed
Full-page burst does not self-terminate.
Can use BURST TERMINATE command. ³
tOH
DOUT m+1
tHZ
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL*
t_{AC (3)}
t_{AC (2)}
t_AH
t_AS
t_CH
t_CL
t_{CK (3)}
t_{CK (2)}
t_CKH
MIN
0.8
1.5
2.5
2.5
7
7.5
0.8
-7E
MAX
5.4
5.4
-75
MIN
0.8
1.5
2.5
2.5
7.5
10
0.8
MAX
5.4
6
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE:
1. For this example, the CAS latency = 2.
2. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
3. Page left open; no ^tRP.
SYMBOL*
t_CKS
t_CMH
t_CMS
t_{HZ (3)}
t_{HZ (2)}
t_LZ
t_OH
t_RCD
MIN
1.5
0.8
1.5
1
3
15
-7E
MAX
5.4
5.4
-75
MIN
1.5
0.8
1.5
1
3
20
MAX
5.4
6
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM.pmd – Rev. H; Pub. 2/05
50
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