MT48LC64M4A2_03 Datasheet, PDF (46/61 Pages) Micron Technology – SYNCHRONOUS DRAM 256Mb: x4, x8, x16 SDRAM

256Mb: x4, x8, x16
SDRAM
Figure 40: Read – With Auto Precharge¹
T0
T1
T2
T3
CLK
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
DQM/
DQML, DQMU
A0-A9, A11, A12
tAS tAH
ROW
NOP
READ
NOP
tCMS tCMH
COLUMN m ²
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
BANK
ENABLE AUTO PRECHARGE
BANK
DQ
tRCD
tRAS
tRC
tAC
tLZ
CAS Latency
T4
T5
T6
NOP
NOP
NOP
tAC
tOH
DOUT m
tAC
tOH
DOUT m + 1
tAC
tOH
DOUT m + 2
tRP
T7
NOP
tOH
DOUT m + 3
tHZ
T8
ACTIVE
ROW
ROW
BANK
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL*
t_{AC (3)}
t_{AC (2)}
t_AH
t_AS
t_CH
t_CL
t_{CK (3)}
t_{CK (2)}
t_CKH
t_CKS
MIN
0.8
1.5
2.5
2.5
7
7.5
0.8
1.5
-7E
MAX
5.4
5.4
-75
MIN
0.8
1.5
2.5
2.5
7.5
10
0.8
1.5
MAX
5.4
6
*CAS latency indicated in parentheses.
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL*
t_CMH
t_CMS
t_{HZ (3)}
t_{HZ (2)}
t_LZ
t_OH
t_RAS
t_RC
t_RCD
t_RP
MIN
0.8
1.5
1
3
37
60
15
15
-7E
MAX
5.4
5.4
120,000
NOTE:
1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
-75
MIN
MAX
0.8
1.5
5.4
6
1
3
44
120,000
66
20
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM.pmd – Rev. H; Pub. 2/05
46
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