MT48LC64M4A2_03 Datasheet, PDF (18/61 Pages) Micron Technology – SYNCHRONOUS DRAM 256Mb: x4, x8, x16 SDRAM

Operation
Bank/Row Activation
Before any READ or WRITE commands can be is-
sued to a bank within the SDRAM, a row in that bank
must be “opened.” This is accomplished via the AC-
TIVE command, which selects both the bank and the
row to be activated (see Figure 9).
After opening a row (issuing an ACTIVE command),
a READ or WRITE command may be issued to that row,
subject to the ^tRCD specification. ^tRCD (MIN) should
be divided by the clock period and rounded up to the
next whole number to determine the earliest clock edge
after the ACTIVE command on which a READ or WRITE
command can be entered. For example, a ^tRCD specifi-
cation of 20ns with a 125 MHz clock (8ns period) results
in 2.5 clocks, rounded to 3. This is reflected in Figure 10,
which covers any case where 2 < ^tRCD (MIN)/^tCK ≤ 3.
(The same procedure is used to convert other specifi-
cation limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row
in the same bank can only be issued after the previous
active row has been “closed” (precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by ^tRC.
A subsequent ACTIVE command to another bank
can be issued while the first bank is being accessed,
which results in a reduction of total row-access over-
head. The minimum time interval between successive
ACTIVE commands to different banks is defined by
t_RRD.
256Mb: x4, x8, x16
SDRAM
Figure 9: Activating a Specific Row in a
Specific Bank
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
A0-A12
BA0, BA1
ROW
ADDRESS
BANK
ADDRESS
Figure 10: Example: Meeting ^tRCD (MIN) When 2 < ^tRCD (MIN)/^tCK ^< 3
T0
T1
T2
T3
T4
CLK
COMMAND
ACTIVE
NOP
NOP
READ or
WRITE
tRCD
DON’T CARE
PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8
256MSDRAM.pmd – Rev. H; Pub. 2/05
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.