MT48LC128M4A2 Datasheet, PDF (48/55 Pages) Micron Technology – SYNCHRONOUS DRAM

ADVANCE
512Mb: x4, x8, x16
SDRAM
WRITE – WITHOUT AUTO PRECHARGE ¹
T0
T1
T2
T3
CLK
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
DQM/
DQML, DQMH
A0-A9, A11, A12
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
ROW
tAS tAH
BANK
tCMS tCMH
COLUMN m³
DISABLE AUTO PRECHARGE
BANK
DQ
tRCD
tRAS
tRC
tDS tDH
DIN m
tDS tDH
DIN m + 1
T4
NOP
tDS tDH
DIN m + 2
T5
NOP
tDS tDH
DIN m + 3
T6
NOP
t _WR ²
T7
T8
PRECHARGE
NOP
ALL BANKs
SINGLE BANK
BANK
tRP
T9
ACTIVE
ROW
ROW
BANK
DON’T CARE
TIMING PARAMETERS
SYMBOL*
t_AH
t_AS
t_CH
t_CL
t_{CK (3)}
t_{CK (2)}
t_CKH
t_CKS
t_CMH
-7E
MIN MAX
0.8
1.5
2.5
2.5
7
7.5
0.8
1.5
0.8
-75
MIN MAX
0.8
1.5
2.5
2.5
7.5
10
0.8
1.5
0.8
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
SYMBOL*
t_CMS
t_DH
t_DS
t_RAS
t_RC
t_RCD
t_RP
t_WR
-7E
MIN MAX
1.5
0.8
1.5
37 120,000
60
15
15
14
-75
MIN MAX UNITS
1.5
ns
0.8
ns
1.5
ns
44 120,000 ns
66
ns
20
ns
20
ns
15
ns
NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.
3. x16: A11 and A12 = “Don’t Care”
x8: A12 = “Don’t Care”
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
48
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.