MT48LC128M4A2 Datasheet, PDF (1/55 Pages) Micron Technology – SYNCHRONOUS DRAM

SYNCHRONOUS
DRAM
ADVANCE^‡
512Mb: x4, x8, x16
SDRAM
MT48LC128M4A2 – 32 Meg x 4 x 4 banks
MT48LC64M8A2 – 16 Meg x 8 x 4 banks
MT48LC32M16A2 – 8 Meg x 16 x 4 banks
For the latest data sheet, please refer to the Micron Web site:
www.micron.com/dramds
FEATURES
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
OPTIONS
• Configurations
128 Meg x 4 (32 Meg x 4 x 4 banks)
64 Meg x 8 (16 Meg x 8 x 4 banks)
32 Meg x 16 (8 Meg x 16 x 4 banks)
• WRITE Recovery (^tWR)
t_{WR = “2 CLK”}1
• Plastic Package – OCPL²
54-pin TSOP II (400 mil)
• Timing (Cycle Time)
7.5ns @ CL = 2 (PC133)
7.5ns @ CL = 3 (PC133)
• Self Refresh
Standard
Low power
• Operating Temperature
Commercial (0^oC to +70^oC)
MARKING
128M4
64M8
32M16
A2
TG
-7E
-75
None
L
None
NOTE: 1. Refer to Micron Technical Note TN-48-05.
2. Off-center parting line.
Part Number Example:
MT48LC32M16A2TG-75
512Mb SDRAM PART NUMBERS
PART NUMBER
MT48LC128M4A2TG
MT48LC64M8A2TG
MT48LC32M16A2TG
ARCHITECTURE
128 Meg x 4
64 Meg x 8
32 Meg x 16
Pin Assignment (Top View)
54-Pin TSOP
x4 x8 x16
- - VDD
1
NC DQ0 DQ0
2
- - VDDQ
3
NC NC DQ1
4
DQ0 DQ1 DQ2
5
- - VssQ
6
NC NC DQ3
7
NC DQ2 DQ4
8
- - VDDQ
9
NC NC DQ5
10
DQ1 DQ3 DQ6
11
- - VssQ
12
NC NC DQ7
13
- - VDD
14
NC NC DQML
15
- - WE#
16
- - CAS#
17
- - RAS#
18
- - CS#
19
- - BA0
20
- - BA1
21
- - A10
22
--
A0
23
--
A1
24
--
A2
25
--
A3
26
- - VDD
27
x16 x8 x4
54
Vss - -
53
DQ15 DQ7 NC
52
VssQ - -
51
DQ14 NC NC
50
DQ13 DQ6 DQ3
49
VDDQ - -
48
DQ12 NC NC
47
DQ11 DQ5 NC
46
VssQ - -
45
DQ10 NC NC
44
DQ9 DQ4 DQ2
43
VDDQ - -
42
DQ8 NC NC
41
Vss - -
40
NC - -
39
DQMH DQM DQM
38
CLK - -
37
CKE - -
36
A12 - -
35
A11 - -
34
A9 - -
33
A8 - -
32
A7 - -
31
A6 - -
30
A5 - -
29
A4 - -
28
Vss - -
NOTE: The # symbol indicates signal is active LOW. A dash
(–) indicates x8 and x4 pin function is same as x16
pin function.
128 Meg x 4
64 Meg x 8
32 Meg x 16
Configuration
32 Meg x 4 x 4 banks 16 Meg x 8 x 4 banks 8 Meg x 16 x 4 banks
Refresh Count
8K
8K
8K
Row Addressing
8K (A0–A12)
8K (A0–A12)
8K (A0–A12)
Bank Addressing
4 (BA0, BA1)
4 (BA0, BA1)
4 (BA0, BA1)
Column Addressing 4K (A0–A9, A11, A12) 2K (A0–A9, A11)
1K (A0–A9)
KEY TIMING PARAMETERS
SPEED
CLOCK
ACCESS TIME SETUP
GRADE FREQUENCY CL = 2* CL = 3* TIME
-7E
143 MHz
–
5.4ns 1.5ns
-75
133 MHz
–
5.4ns 1.5ns
-7E
133 MHz 5.4ns
–
1.5ns
-75
100 MHz
6ns
–
1.5ns
HOLD
TIME
0.8ns
0.8ns
0.8ns
0.8ns
*CL = CAS (READ) latency
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE
BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.