MT48LC128M4A2 Datasheet, PDF (19/55 Pages) Micron Technology – SYNCHRONOUS DRAM

A fixed-length READ burst may be followed by, or
truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not activated),
and a full-page burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in Figure 11 for each possible CAS latency; data
ADVANCE
512Mb: x4, x8, x16
SDRAM
element n + 3 is either the last of a burst of four or the last
desired of a longer burst. Following the PRECHARGE
command, a subsequent command to the same bank
cannot be issued until ^tRP is met. Note that part of the row
precharge time is hidden during the access of the last
data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the opti-
mum time (as described above) provides the same op-
T0
T1
CLK
COMMAND
READ
NOP
ADDRESS
BANK a,
COL n
T2
NOP
T3
T4
T5
T6
t _RP
NOP
PRECHARGE
NOP
NOP
X = 1 cycle
BANK
(a or all)
T7
ACTIVE
BANK a,
ROW
DQ
CAS Latency = 2
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
T0
T1
CLK
COMMAND
READ
NOP
ADDRESS
BANK a,
COL n
T2
NOP
T3
T4
T5
T6
t _RP
NOP
PRECHARGE
NOP
NOP
BANK
(a or all)
X = 2 cycles
T7
ACTIVE
BANK a,
ROW
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
CAS Latency = 3
NOTE: DQM is LOW.
Figure 11
READ to PRECHARGE
DOUT
n+3
DON’T CARE
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.