MT28S4M16LC Datasheet, PDF (39/48 Pages) Micron Technology – SYNCFLASH MEMORY

4 MEG x 16
SYNCFLASH MEMORY
INITIALIZE AND LOAD MODE REGISTER
T0
CLK
tCKS tCKH
CKE
COMMAND
T1
Tn+1
((
))
((
))
((
))
((
))
((
))
((
))
tCKTn ^{+ 2}
tCH
Tn + 3
tCL
tCMH tCMS
LOAD MODE
REGISTER
NOP
((
DQM
))
((
))
((
VCC, VCCP,
))
VCCQ
((
RP#1
))
ADDRESS
DQ
tAS tAH
((
))
((
OPCODE
))
High-Z
((
))
tMRD
T = 100µs
Power-up:²
Program Mode Register^{3, 4, 5}
VCC, VCCP, VCCQ,
CLK stable
Tn + 4
ACTIVE
ROW
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL*
t_AH
t_AS
t_CH
t_CL
t_{CK (3)}
t_{CK (2)}
-10
MIN
MAX
2
3
3.5
3.5
10
15
-12
MIN
MAX
2
3
4
4
12
15
*CAS latency indicated in parentheses.
UNITS
ns
ns
ns
ns
ns
ns
SYMBOL*
t_{CK (1)}
t_CKH
t_CKS
t_CMH
t_CMS
t_MRD
-10
MIN
MAX
30
2
3
2
3
2
-12
MIN
MAX
30
2
3
2
3
2
UNITS
ns
ns
ns
ns
ns
t_CK
NOTE:
1. RP# = VHH or VIH
2. VCC, VCCP, VCCQ = 3.3V
3. The nvmode register contents are automatically loaded into the mode register upon power-up initialization, LOAD
MODE REGISTER cycle is required to enter new mode register values.
4. JEDEC and PC100 specify three clocks.
5. If CS is HIGH at clock time, all commands applied are NOP, with CKE a “Don’t Care.”
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
39
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©2001, Micron Technology, Inc.