MT28S4M16LC Datasheet, PDF (1/48 Pages) Micron Technology – SYNCFLASH MEMORY

SYNCFLASH^®
MEMORY
4 MEG x 16
SYNCFLASH MEMORY
MT28S4M16LC
1 Meg x 16 x 4 banks
FEATURES
• 100 MHz SDRAM-compatible read timing
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access
• Programmable burst lengths: 1, 2, 4, 8, or full page
(READ)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
– Additional VHH hardware protect mode (RP#)
• Four-bank architecture supports true concurrent
operations with zero latency:
Read from any bank while performing a
PROGRAM or ERASE operation to any other
bank
• Deep power-down mode: 300µA maximum
• Cross-compatible Flash memory command set
• Industry-standard, SDRAM-compatible pinouts
– Pins 36 and 40 are no connects for SDRAM
OPTIONS
• Configuration
4 Meg x 16 (1 Meg x 16 x 4 banks)
MARKING
4M16
• Read Timing (Cycle Time)
10ns (100 MHz)
-10
12ns (83 MHz)
-12
• Package
54-pin OCPL¹ TSOP II (400 mil)
TG
• Operating Temperature Range
Commercial Temperature (0ºC to +70ºC) None
NOTE: 1. Off-center parting line
Part Number Example:
MT28S4M16LCTG-10
GENERAL DESCRIPTION
This SyncFlash^® data sheet is divided into two ma-
jor sections. The SDRAM Interface Functional
Description details compatibility with the SDRAM
memory, and the Flash Memory Functional Descrip-
tion specifies the symmetrical-sectored flash architec-
ture functional commands.
PIN ASSIGNMENT (Top View)
54-Pin TSOP II
VCC
1
DQ0
2
VCCQ
3
DQ1
4
DQ2
5
VSSQ
6
DQ3
7
DQ4
8
VCCQ
9
DQ5
10
DQ6
11
VSSQ
12
DQ7
13
VCC
14
DQML
15
WE#
16
CAS#
17
RAS#
18
CS#
19
BA0
20
BA1
21
A10
22
A0
23
A1
24
A2
25
A3
26
VCC
27
54
VSS
53
DQ15
52
VSSQ
51
DQ14
50
DQ13
49
VCCQ
48
DQ12
47
DQ11
46
VSSQ
45
DQ10
44
DQ9
43
VCCQ
42
DQ8
41
VSS
40
RP#
39
DQMH
38
CLK
37
CKE
36
VCCP
35
A11
34
A9
33
A8
32
A7
31
A6
30
A5
29
A4
28
VSS
NOTE: The # symbol indicates signal is active LOW.
KEY TIMING PARAMETERS
SPEED
GRADE
-10
-10
-12
-12
CLOCK
ACCESS TIME
FREQUENCY CL = 2* CL = 3*
100 MHz
–
7ns
66 MHz
9ns
–
83 MHz
–
9ns
66 MHz
10ns
–
SETUP
TIME
3ns
3ns
3ns
3ns
*CL = CAS (READ) latency
HOLD
TIME
2ns
2ns
2ns
2ns
The MT28S4M16LC is a nonvolatile, electrically sec-
tor-erasable (Flash), programmable memory contain-
ing 67,108,864 bits organized as 4,194,304 words (16
bits). SyncFlash memory is ideal for 3.3V-only plat-
forms that require both hardware and software protec-
tion modes. Additional hardware protection modes are
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 – Rev. 6, Pub. 9/01
1
©2001, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.