M25P40-VMP6TGB Datasheet, PDF (34/54 Pages) Micron Technology – M25P40 3V 4Mb Serial Flash Embedded Memory

M25P40 Serial Flash Embedded Memory
Power-Up/Down and Supply Line Decoupling
Figure 21: Power-Up Timing
VCC
VCC,max
PROGRAM, ERASE, and WRITE commands are rejected by the device
Chip selection not allowed
VCC,min
VWI
RESET state
of the
device
t_VSL
READ access allowed
t_PUW
Device fully
accessible
Time
After power-up, the device is in the following state:
• Standby power mode (not the deep power-down mode)
• Write enable latch (WEL) bit is reset
• Write in progress (WIP) bit is reset
• Write lock bit = 0
• Lock down bit = 0
Normal precautions must be taken for supply line decoupling to stabilize the V_CC sup-
ply. Each device in a system should have the V_CC line decoupled by a suitable capacitor
close to the package pins; generally, this capacitor is of the order of 100 nF.
At power-down, when V_CC drops from the operating voltage to below the POR threshold
voltage V_WI, all operations are disabled and the device does not respond to any instruc-
tion.
Note: If power-down occurs while a WRITE, PROGRAM, or ERASE cycle is in progress,
some data corruption may result.
PDF: 09005aef8456654f
m25p40.pdf - Rev. G 05/13 EN
34
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