M25P40-VMP6TGB Datasheet, PDF (13/54 Pages) Micron Technology – M25P40 3V 4Mb Serial Flash Embedded Memory

Hold Condition
M25P40 Serial Flash Embedded Memory
Operating Features
The HOLD# signal is used to pause any serial communications with the device without
resetting the clocking sequence. However, taking this signal LOW does not terminate
any WRITE STATUS REGISTER, PROGRAM, or ERASE cycle that is currently in progress.
To enter the hold condition, the device must be selected, with S# LOW. The hold condi-
tion starts on the falling edge of the HOLD# signal, if this coincides with serial clock (C)
being LOW. The hold condition ends on the rising edge of the HOLD# signal, if this co-
incides with C being LOW. If the falling edge does not coincide with C being LOW, the
hold condition starts after C next goes LOW. Similarly, if the rising edge does not coin-
cide with C being LOW, the hold condition ends after C next goes LOW.
During the hold condition, DQ1 is HIGH impedance while DQ0 and C are Don’t Care.
Typically, the device remains selected with S# driven LOW for the duration of the hold
condition. This ensures that the state of the internal logic remains unchanged from the
moment of entering the hold condition. If S# goes HIGH while the device is in the hold
condition, the internal logic of the device is reset. To restart communication with the
device, it is necessary to drive HOLD# HIGH, and then to drive S# LOW. This prevents
the device from going back to the hold condition.
Figure 5: Hold Condition Activation
C
HOLD#
HOLD condition (standard use)
HOLD condition (nonstandard use)
PDF: 09005aef8456654f
m25p40.pdf - Rev. G 05/13 EN
13
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