M25P40-VMP6TGB Datasheet, PDF (33/54 Pages) Micron Technology – M25P40 3V 4Mb Serial Flash Embedded Memory

M25P40 Serial Flash Embedded Memory
Power-Up/Down and Supply Line Decoupling
Power-Up/Down and Supply Line Decoupling
At power-up and power-down, the device must not be selected; that is, chip select (S#)
must follow the voltage applied on V_CC until V_CC reaches the correct value:
• V_CC,min at power-up, and then for a further delay of t_VSL
• V_SS at power-down
A safe configuration is provided in the SPI Modes section.
To avoid data corruption and inadvertent write operations during power-up, a power-
on-reset (POR) circuit is included. The logic inside the device is held reset while V_CC is
less than the POR threshold voltage, V_WI – all operations are disabled, and the device
does not respond to any instruction. Moreover, the device ignores the following instruc-
tions until a time delay of ^tPUW has elapsed after the moment that V_CC rises above the
V_WI threshold:
• WRITE ENABLE
• PAGE PROGRAM
• SECTOR ERASE
• BULK ERASE
• WRITE STATUS REGISTER
However, the correct operation of the device is not guaranteed if, by this time, V_CC is still
below V_CC.min. No WRITE STATUS REGISTER, PROGRAM, or ERASE instruction should
be sent until:
• ^tPUW after V_CC has passed the V_WI threshold
• ^tVSL after V_CC has passed the V_CC,min level
If the time, ^tVSL, has elapsed, after V_CC rises above V_CC,min, the device can be selected
for READ instructions even if the ^tPUW delay has not yet fully elapsed.
V_PPH must be applied only when V_CC is stable and in the V_CC,min to V_CC,max voltage
range.
PDF: 09005aef8456654f
m25p40.pdf - Rev. G 05/13 EN
33
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