MT48LC32M16A2P-75ITC Datasheet, PDF (28/77 Pages) Micron Technology – SDR SDRAM MT48LC128M4A2 – 32 Meg x 4 x 4 banks MT48LC64M8A2 – 16 Meg x 8 x 4 banks MT48LC32M16A2 – 8 Meg x 16 x 4 banks

Truth Tables
512Mb: x4, x8, x16 SDRAM
Truth Tables
Table 14: Truth Table – Current State Bank n, Command to Bank n
Notes 1–6 apply to all parameters and conditions
Current State
CS# RAS# CAS#
Any
H
X
X
L
H
H
Idle
L
L
H
L
L
L
L
L
L
L
L
H
Row active
L
H
L
L
H
L
L
L
H
Read
L
H
L
(auto precharge disabled) _L
H
L
L
L
H
L
H
H
Write
L
H
L
(auto precharge disabled) _L
H
L
L
L
H
L
H
H
WE# Command/Action
X COMMAND INHIBIT (NOP/continue previous operation)
H NO OPERATION (NOP/continue previous operation)
H ACTIVE (select and activate row)
H AUTO REFRESH
L LOAD MODE REGISTER
L PRECHARGE
H READ (select column and start READ burst)
L WRITE (select column and start WRITE burst)
L PRECHARGE (deactivate row in bank or banks)
H READ (select column and start new READ burst)
L WRITE (select column and start WRITE burst)
L PRECHARGE (truncate READ burst, start PRECHARGE)
L BURST TERMINATE
H READ (select column and start READ burst)
L WRITE (select column and start new WRITE burst)
L PRECHARGE (truncate WRITE burst, start PRECHARGE)
L BURST TERMINATE
Notes
7
7
8
9
9
10
9
9
10
11
9
9
10
11
Notes:
1. This table applies when CKE_n-1 was HIGH and CKE_n is HIGH (see Table 16 (page 32))
and after ^tXSR has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted (for example, the current state is for a
specific bank and the commands shown can be issued to that bank when in that state).
Exceptions are covered below.
3. Current state definitions:
Idle: The bank has been precharged, and ^tRP has been met.
Row active: A row in the bank has been activated, and ^tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank.
COMMAND INHIBIT or NOP commands, or supported commands to the other bank
should be issued on any clock edge occurring during these states. Supported commands
to any other bank are determined by the bank’s current state and the conditions descri-
bed in this and the following table.
Precharging: Starts with registration of a PRECHARGE command and ends when ^tRP is
met. After ^tRP is met, the bank will be in the idle state.
Row activating: Starts with registration of an ACTIVE command and ends when ^tRCD is
met. After ^tRCD is met, the bank will be in the row active state.
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