MT48LC32M16A2P-75ITC Datasheet, PDF (11/77 Pages) Micron Technology – SDR SDRAM MT48LC128M4A2 – 32 Meg x 4 x 4 banks MT48LC64M8A2 – 16 Meg x 8 x 4 banks MT48LC32M16A2 – 8 Meg x 16 x 4 banks

512Mb: x4, x8, x16 SDRAM
Pin and Ball Assignments and Descriptions
Table 4: Pin and Ball Descriptions
Symbol
CLK
CKE
CS#
CAS#, RAS#,
WE#
x4, x8:
DQM
x16:
DQML, DQMH
LDQM, UDQM
(54-ball)
BA[1:0]
A[12:0]
x16:
DQ[15:0]
x8:
DQ[7:0]
x4:
DQ[3:0]
V_DDQ
V_SSQ
V_DD
V_SS
NC
Type
Input
Input
Input
Input
Description
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive
edge of CLK. CLK also increments the internal burst counter and controls the output registers.
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the
clock provides precharge power-down and SELF REFRESH operation (all banks idle), active
power-down (row active in any bank), or CLOCK SUSPEND operation (burst/access in pro-
gress). CKE is synchronous except after the device enters power-down and self refresh modes,
where CKE becomes asynchronous until after exiting the same mode. The input buffers, in-
cluding CLK, are disabled during power-down and self refresh modes, providing low standby
power. CKE may be tied HIGH.
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decod-
er. All commands are masked when CS# is registered HIGH, but READ/WRITE bursts already in
progress will continue, and DQM operation will retain its DQ mask capability while CS# is
HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is consid-
ered part of the command code.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered.
Input
Input/output mask: DQM is an input mask signal for write accesses and an output enable sig-
nal for read accesses. Input data is masked when DQM is sampled HIGH during a WRITE cycle.
The output buffers are placed in a High-Z state (two-clock latency) when DQM is sampled
HIGH during a READ cycle. On the x4 and x8, DQML (pin 15) is a NC and DQMH is DQM. On
the x16, DQML corresponds to DQ[7:0], and DQMH corresponds to DQ[15:8]. DQML and
DQMH are considered same state when referenced as DQM.
Input
Input
I/O
I/O
Bank address input(s): BA[1:0] define to which bank the ACTIVE, READ, WRITE, or PRECHARGE
command is being applied.
Address inputs: A[12:0] are sampled during the ACTIVE command (row address A[12:0]) and
READ or WRITE command (column address A[9:0], A11, and A12 for x4; A[9:0] and A11 for x8;
A[9:0] for x16; with A10 defining auto precharge) to select one location out of the memory
array in the respective bank. A10 is sampled during a PRECHARGE command to determine if
all banks are to be precharged (A10 HIGH) or bank selected by A10 (LOW). The address inputs
also provide the op-code during a LOAD MODE REGISTER command.
Data input/output: Data bus for x16 (pins 4, 7, 10, 13, 15, 42, 45, 48, and 51 are NC for x8; and
pins 2, 4, 7, 8, 10, 13, 15, 42, 45, 47, 48, 51, and 53 are NC for x4).
Data input/output: Data bus for x8 (pins 2, 8, 47, 53 are NC for x4).
I/O Data input/output: Data bus for x4.
Supply
Supply
Supply
Supply
–
DQ power: DQ power to the die for improved noise immunity.
DQ ground: DQ ground to the die for improved noise immunity.
Power supply: +3.3V ±0.3V.
Ground.
These should be left unconnected.
PDF: 09005aef809bf8f3
512Mb_sdr.pdf - Rev. Q 12/12 EN
11
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