MT47H128M16RT-25EC Datasheet, PDF (28/134 Pages) Micron Technology – DDR2 SDRAM MT47H512M4 – 64 Meg x 4 x 8 banks MT47H256M8 – 32 Meg x 8 x 8 banks MT47H128M16 – 16 Meg x 16 x 8 banks

2Gb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – I_DD Parameters
Table 10: DDR2 I_DD Specifications and Conditions (Die Revision A)
Notes 1–7 apply to the entire table
Parameter/Condition
Symbol Configuration -25E/-25 -3
Operating one bank active-precharge current:
I_DD0
t_{CK =} t_{CK (IDD),} t_{RC =} t_{RC (IDD),} t_{RAS =} t_{RAS MIN (IDD); CKE is}
HIGH, CS# is HIGH between valid commands; Address bus in-
puts are switching; Data bus inputs are switching
x4, x8
x16
115
100
150
135
Operating one bank active-read-precharge current:
Iout = 0mA; BL = 4, CL = CL (I_DD), AL = 0; ^tCK = ^tCK (I_DD), ^tRC =
t_{RC (IDD),} t_{RAS =} t_{RAS MIN (IDD),} t_{RCD =} t_{RCD (IDD); CKE is HIGH,}
CS# is HIGH between valid commands; Address bus inputs are
switching; Data pattern is same as I_DD4W
Precharge power-down current: All banks idle; ^tCK = ^tCK
(I_DD); CKE is LOW; Other control and address bus inputs are sta-
ble; Data bus inputs are floating
I_DD1
I_DD2P
x4, x8
x16
x4, x8, x16
165
145
180
160
12
12
Precharge quiet standby current: All banks idle; ^tCK = ^tCK
(I_DD); CKE is HIGH, CS# is HIGH; Other control and address bus
inputs are stable; Data bus inputs are floating
I_DD2Q
x4, x8
x16
65
55
75
65
Precharge standby current: All banks idle; ^tCK = ^tCK (I_DD);
CKE is HIGH, CS# is HIGH; Other control and address bus inputs
are switching; Data bus inputs are switching
I_DD2N
x4, x8
x16
70
60
80
70
Active power-down current: All banks open; ^tCK = ^tCK (I_DD); I_DD3Pf
Fast PDN exit
45
40
CKE is LOW; Other control and address bus inputs are stable;
MR[12] = 0
Data bus inputs are floating
I_DD3Ps
Slow PDN exit
14
14
MR[12] = 1
Active standby current: All banks open; ^tCK = ^tCK (I_DD), ^tRAS
= ^tRAS MAX (I_DD), ^tRP = ^tRP (I_DD); CKE is HIGH, CS# is HIGH be-
tween valid commands; Other control and address bus inputs
are switching; Data bus inputs are switching
I_DD3N
x4, x8
x16
65
55
85
75
Operating burst write current: All banks open, continuous
burst writes; BL = 4, CL = CL (I_DD), AL = 0; ^tCK = ^tCK (I_DD), ^tRAS =
t_{RAS MAX (IDD),} t_{RP =} t_{RP (IDD); CKE is HIGH, CS# is HIGH be-}
tween valid commands; Address bus inputs are switching; Data
bus inputs are switching
I_DD4W
x4, x8
x16
180
160
270
250
Operating burst read current: All banks open, continuous
burst reads, I_OUT = 0mA; BL = 4, CL = CL (I_DD), AL = 0; ^tCK = ^tCK
(I_DD), ^tRAS = ^tRAS MAX (I_DD), ^tRP = ^tRP (I_DD); CKE is HIGH, CS# is
HIGH between valid commands; Address bus inputs are switch-
ing; Data bus inputs are switching
I_DD4R
x4, x8
x16
190
170
295
275
Burst refresh current: ^tCK = ^tCK (I_DD); refresh command at
I_DD5
every ^tRFC (I_DD) interval; CKE is HIGH, CS# is HIGH between val-
id commands; Other control and address bus inputs are switch-
ing; Data bus inputs are switching
x4, x8
x16
300
280
300
280
Self refresh current: CK and CK# at 0V; CKE ื 0.2V; Other
control and address bus inputs are floating; Data bus inputs
are floating
I_DD6
I_DD6L
x4, x8, x16
12
12
8
8
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
PDF: 09005aef824f87b6
2Gb_DDR2.pdf – Rev. H 10/11 EN
28
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