MT47H128M16RT-25EC Datasheet, PDF (126/134 Pages) Micron Technology – DDR2 SDRAM MT47H512M4 – 64 Meg x 4 x 8 banks MT47H256M8 – 32 Meg x 8 x 8 banks MT47H128M16 – 16 Meg x 16 x 8 banks

2Gb: x4, x8, x16 DDR2 SDRAM
Reset
3. Minimum CKE high time is ^tCKE = 3 × ^tCK. Minimum CKE LOW time is ^tCKE = 3 × ^tCK.
This requires a minimum of three clock cycles of registration.
4. If this command is a PRECHARGE (or if the device is already in the idle state), then the
power-down mode shown is precharge power-down, which is required prior to the clock
frequency change.
Reset
CKE Low Anytime
DDR2 SDRAM applications may go into a reset state anytime during normal operation.
If an application enters a reset condition, CKE is used to ensure the DDR2 SDRAM de-
vice resumes normal operation after reinitializing. All data will be lost during a reset
condition; however, the DDR2 SDRAM device will continue to operate properly if the
following conditions outlined in this section are satisfied.
The reset condition defined here assumes all supply voltages (V_DD, V_DDQ, V_DDL, and
V_REF) are stable and meet all DC specifications prior to, during, and after the RESET op-
eration. All other input balls of the DDR2 SDRAM device are a “Don’t Care” during RE-
SET with the exception of CKE.
If CKE asynchronously drops LOW during any valid operation (including a READ or
WRITE burst), the memory controller must satisfy the timing parameter ^tDELAY before
turning off the clocks. Stable clocks must exist at the CK, CK# inputs of the DRAM be-
fore CKE is raised HIGH, at which time the normal initialization sequence must occur
(see Initialization). The DDR2 SDRAM device is now ready for normal operation after
the initialization sequence. Figure 80 (page 127) shows the proper sequence for a RE-
SET operation.
PDF: 09005aef824f87b6
2Gb_DDR2.pdf – Rev. H 10/11 EN
126
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