MT47H128M16RT-25EC Datasheet, PDF (112/134 Pages) Micron Technology – DDR2 SDRAM MT47H512M4 – 64 Meg x 4 x 8 banks MT47H256M8 – 32 Meg x 8 x 8 banks MT47H128M16 – 16 Meg x 16 x 8 banks

2Gb: x4, x8, x16 DDR2 SDRAM
WRITE
Figure 65: Bank Write – with Auto Precharge
T0
CK#
CK
CKE
Command
NOP1
Address
A10
T1
T2
T3
T4
tCK
tCH tCL
ACT
NOP1
WRITE2
NOP1
RA
Col n
3
RA
T5 T5n T6 T6n T7
NOP1
NOP1
NOP1
T8
T9
NOP1
NOP1
Bank select
DQS, DQS#
DQ6
DM
Bank x
tRCD
Bank x
WL = 2
tRAS
WL ±tDQSS (NOM)
5
WR4
tRP
tWPRE
DI
n
tDQSL tDQSH tWPST
Transitioning Data
Don’t Care
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4 and AL = 0 in the case shown.
3. Enable auto precharge.
4. WR is programmed via MR9–MR11 and is calculated by dividing ^tWR (in ns) by ^tCK and
rounding up to the next integer value.
5. Subsequent rising DQS signals must align to the clock within ^tDQSS.
6. DI n = data-in from column n; subsequent elements are applied in the programmed or-
der.
7. ^tDSH is applicable during ^tDQSS (MIN) and is referenced from CK T5 or T6.
8. ^tDSS is applicable during ^tDQSS (MAX) and is referenced from CK T6 or T7.
PDF: 09005aef824f87b6
2Gb_DDR2.pdf – Rev. H 10/11 EN
112
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