MT41J256M8HX-187ED Datasheet, PDF (197/211 Pages) Micron Technology – 2Gb: x4, x8, x16 DDR3 SDRAM Features

2Gb: x4, x8, x16 DDR3 SDRAM
Dynamic ODT
Figure 111: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4
T0
CK#
CK
Command NOP
Address
ODT
R_TT
DQS, DQS#
DQ
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
WRS4
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ODTLcnw
Valid
ODTH4
ODTLoff
ODTLon
t_{ADC (MAX)}
t_{AON (MIN)}
R_TT(WR)
ODTLcwn4
t_{ADC (MIN)}
R_TT,nom
t_{ADC (MAX)}
t_{AOF (MIN)}
t_{AOF (MAX)}
DI
DI DI
DI
n n+1 n+2 n+3
WL
Transitioning
Don’t Care
Notes: 1. Via MRS or OTF. AL = 0, CWL = 5. R_TT,nom and R_TT(WR) are enabled.
2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW, so in this example,
ODTH4 is satisfied. ODT registered LOW at T5 is also legal.
Figure 112: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
T0
CK#
CK
Command NOP
Address
ODT
R_TT
DQS, DQS#
DQ
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
WRS4
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ODTLcnw
Valid
ODTH4
ODTLoff
ODTLon
t_{ADC (MAX)}
t_{AON (MIN)}
ODTLcwn4
R_TT(WR)
t_{AOF (MIN)}
t_{AOF (MAX)}
WL
DI
DI DI DI
n n+1 n+2 n+3
Transitioning
Don’t Care
Notes: 1. Via MRS or OTF. AL = 0, CWL = 5. R_TT,nom can be either enabled or disabled. If disabled,
ODT can remain HIGH. R_TT(WR) is enabled.
2. In this example ODTH4 = 4 is satisfied exactly.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN
197
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