MT41J256M8HX-187ED Datasheet, PDF (147/211 Pages) Micron Technology – 2Gb: x4, x8, x16 DDR3 SDRAM Features

2Gb: x4, x8, x16 DDR3 SDRAM
Mode Register 3 (MR3)
• Burst order bit 0 (the first bit) is assigned to LSB, and burst order bit 7 (the last bit) is
assigned to MSB.
• A[9:3] are “Don’t Care.”
• A10 is “Don’t Care.”
• A11 is “Don’t Care.”
• A12: Selects burst chop mode on-the-fly, if enabled within MR0.
• A13 is a “Don’t Care”
• BA[2:0] are “Don’t Care.”
MPR Address Definitions and Bursting Order
The MPR currently supports a single data format. This data format is a predefined read
pattern for system calibration. The predefined pattern is always a repeating 01 bit pat-
tern.
Examples of the different types of predefined READ pattern bursts are shown in the fol-
lowing figures.
Table 78: MPR Readouts and Burst Order Bit Mapping
MR3[2]
1
MR3[1:0]
00
Function
READ predefined pattern
for system calibration
Burst
Length
BL8
BC4
Read
A[2:0]
000
000
BC4
100
1
01
RFU
n/a
n/a
n/a
n/a
n/a
n/a
1
10
RFU
n/a
n/a
n/a
n/a
n/a
n/a
1
11
RFU
n/a
n/a
n/a
n/a
n/a
n/a
Burst Order and Data Pattern
Burst order: 0, 1, 2, 3, 4, 5, 6, 7
Predefined pattern: 01010101
Burst order: 0, 1, 2, 3
Predefined pattern: 0101
Burst order: 4, 5, 6, 7
Predefined pattern: 0101
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Note: 1. Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selec-
ted MPR agent.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN
147
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2006 Micron Technology, Inc. All rights reserved.