MT41J256M8HX-187ED Datasheet, PDF (141/211 Pages) Micron Technology – 2Gb: x4, x8, x16 DDR3 SDRAM Features

2Gb: x4, x8, x16 DDR3 SDRAM
Mode Register 1 (MR1)
internally to the DDR3 SDRAM device. READ latency (RL) is controlled by the sum of
the AL and CAS latency (CL), RL = AL + CL. WRITE latency (WL) is the sum of CAS
WRITE latency and AL, WL = AL + CWL (see Mode Register 2 (MR2) (page 142)). Exam-
ples of READ and WRITE latencies are shown in Figure 54 (page 141) and Figure 55
(page 142).
Figure 54: READ Latency (AL = 5, CL = 6)
BC4
CK#
CK
Command
T0
ACTIVE n
DQS, DQS#
DQ
T1
T2
READ n
NOP
t_{RCD (MIN)}
AL = 5
T6
T11
NOP
NOP
CL = 6
RL = AL + CL = 11
T12
T13
T14
NOP
NOP
NOP
DO
DO
DO
DO
n
n+1
n+2
n+3
Indicates break
in time scale
Transitioning Data
Don’t Care
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN
141
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