MT4LC8M8P4 Datasheet, PDF (17/22 Pages) Micron Technology – DRAM

RAS#
V
V
IH
IL
CAS# ^VIH
V _IL
V _IH
ADDR VIL
WE#
V
V
IH
IL
DQ
V _OH
V _OL
OE#
V
V
IH
IL
READ CYCLE
(with WE#-controlled disable)
8 MEG x 8
EDO DRAM
tCRP
tRCD
tCSH
tCAS
tASR
tRAD
tRAH
ROW
tAR
tASC
tCAH
tRCS
COLUMN
OPEN
tAA
tRAC
tCAC
tCLZ
tOE
tCP
tASC
tRCH
tWPZ
COLUMN
tRCS
tWHZ
VALID DATA
tOD
tCLZ
OPEN
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL
t_AA
t_AR
t_ASC
t_ASR
t_CAC
t_CAH
t_CAS
t_CLZ
t_CP
t_CRP
t_CSH
MIN
38
0
0
8
8
0
8
5
38
-5
MAX
25
13
10,000
MIN
45
0
0
10
10
0
10
5
45
-6
MAX
30
15
10,000
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
t_OD
t_OE
t_RAC
t_RAD
t_RAH
t_RCD
t_RCH
t_RCS
t_WHZ
t_WPZ
-5
MIN
MAX
0
12
12
50
9
9
11
0
0
12
10
-6
MIN
MAX
0
15
15
60
12
10
14
0
0
15
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8 Meg x 8 EDO DRAM
D20_2.p65 – Rev. 5/00
17
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