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MT4LC8M8P4 Datasheet, PDF (13/22 Pages) Micron Technology – DRAM
RAS#
V IH
V IL
CAS# VIH
V IL
ADDR
V
V
IH
IL
WE# VIH
V IL
DQ VVOOHL
OE#
V IH
V IL
EDO-PAGE-MODE READ CYCLE
tRASP
8 MEG x 8
EDO DRAM
tRP
tCSH
tPC
tRSH
tCRP
tRCD
tCAS
tCP
tCAS
tCP
tCAS
tCP
tASR
tRAD
tRAH
ROW
tAR
tACH
tASC
tCAH
COLUMN
tRCS
OPEN
tAA
tRAC
tCAC
tCLZ
tOE
tOES
tACH
tASC
tCAH
COLUMN
tACH
tASC
tCAH
COLUMN
VALID
DATA
tAA
tCPA
tCAC
tCOH
tCLZ
tOEHC
VALID
DATA
tOD
tOEP
tAA
tCPA
tCAC
tOE
tOES
ROW
tRCH
tRRH
tOFF
VALID
DATA
OPEN
tOD
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL
tAA
tACH
tAR
tASC
tASR
tCAC
tCAH
tCAS
tCLZ
tCOH
tCP
tCPA
tCRP
tCSH
tOD
tOE
MIN
12
38
0
0
8
8
0
3
8
5
38
0
-5
MAX
25
13
10,000
28
12
12
MIN
15
45
0
0
10
10
0
3
10
5
45
0
-6
MAX
30
15
10,000
35
15
15
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
tOEHC
tOEP
tOES
tOFF
tPC
tRAC
tRAD
tRAH
tRASP
tRCD
tRCH
tRCS
tRP
tRRH
tRSH
MIN
5
5
4
0
20
9
9
50
11
0
0
30
0
13
-5
MAX
12
50
125,000
MIN
10
5
5
0
25
12
10
60
14
0
0
40
0
15
-6
MAX
15
60
125,000
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8 Meg x 8 EDO DRAM
D20_2.p65 – Rev. 5/00
13
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©2000, Micron Technology, Inc.