MT4LC8M8P4 Datasheet, PDF (1/22 Pages) Micron Technology – DRAM

DRAM
8 MEG x 8
EDO DRAM
MT4LC8M8P4, MT4LC8M8C2
For the latest data sheet, please refer to the Micron Web
site: www.micronsemi.com/mti/msp/html/datasheet.html
FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x8 pinout, timing, functions,
and packages
• 12 row, 11 column addresses (C2) or
13 row, 10 column addresses (P4)
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-
compatible
• Extended Data-Out (EDO) PAGE MODE access
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms
• Optional self refresh (S) for low-power data
retention
OPTIONS
• Refresh Addressing
4,096 (4K) rows
8,192 (8K) rows
MARKING
C2
P4
• Plastic Packages
32-pin SOJ (400 mil)
DJ
32-pin TSOP (400 mil)
TG
• Timing
50ns access
-5
60ns access
-6
• Refresh Rates
Standard Refresh (64ms period)
Self Refresh (128ms period)
None
S*
NOTE: 1. The 8 Meg x 8 EDO DRAM base number
differentiates the offerings in one place—
MT4LC8M8C2. The fifth field distinguishes the
address offerings: C2 designates 4K addresses and
P4 designates 8K addresses.
2. The “#” symbol indicates signal is active LOW.
*Contact factory for availability
Part Number Example:
MT4LC8M8C2DJ-5
KEY TIMING PARAMETERS
SPEED
-5
-6
t_RC
84ns
104ns
t_RAC
50ns
60ns
t_PC
20ns
25ns
t_AA
25ns
30ns
t_CAC
13ns
15ns
t_CAS
8ns
10ns
PIN ASSIGNMENT (Top View)
32-Pin SOJ
32-Pin TSOP
VCC 1
DQ0 2
DQ1 3
DQ2 4
DQ3 5
NC 6
VCC 7
WE# 8
RAS# 9
A0 10
A1 11
A2 12
A3 13
A4 14
A5 15
VCC 16
32 VSS
31 DQ7
30 DQ6
29 DQ5
28 DQ4
27 Vss
26 CAS#
VCC 1
DQ0 2
DQ1 3
DQ2 4
DQ3 5
NC 6
VCC 7
WE# 8
25 OE#
RAS# 9
24 NC/A12** ^{A0 10}
23 A11
A1 11
22 A10
21 A9
20 A8
19 A7
A2 12
A3 13
A4 14
A5 15
VCC 16
18 A6
17 VSS
**NC on C2 version and A12 on P4 version
32 VSS
31 DQ7
30 DQ6
29 DQ5
28 DQ4
27 VSS
26 CAS#
25 OE#
24 NC/A12**
23 A11
22 A10
21 A9
20 A8
19 A7
18 A6
17 VSS
8 MEG x 8 EDO DRAM PART NUMBERS
PART NUMBER
MT4LC8M8C2DJ-x
MT4LC8M8C2DJ-x S
MT4LC8M8C2TG-x
MT4LC8M8C2TG-x S
MT4LC8M8P4DJ-x
MT4LC8M8P4DJ-x S
MT4LC8M8P4TG-x
MT4LC8M8P4TG-x S
REFRESH
ADDRESSING
4K
4K
4K
4K
8K
8K
8K
8K
PACKAGE REFRESH
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
Standard
Self
Standard
Self
Standard
Self
Standard
Self
x = speed
GENERAL DESCRIPTION
The 8 Meg x 8 DRAM is a high-speed CMOS, dy-
namic random-access memory devices containing
67,108,864 bits and designed to operate from 3V to
3.6V. The MT4LC8M8C2 and MT4LC8M8P4 are func-
tionally organized as 8,388,608 locations containing
eight bits each. The 8,388,608 memory locations are
arranged in 4,096 rows by 2,048 columns on the C2
version and 8,192 rows by 1,024 columns on the P4
version. During READ or WRITE cycles, each location is
8 Meg x 8 EDO DRAM
D20_2.p65 – Rev. 5/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.