MT29F8G08DAAWCA Datasheet, PDF (14/81 Pages) Micron Technology – 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory

4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
Array Organization
Figure 7: Array Organization for MT29F8G08BAA and MT29F16G08FAA (x8)
Die 0
Die 1
Cache Register
Data Register
2,112 bytes
2,112 bytes
2,048
64
2,048
64
2,048
64
2,048
64
2,112 bytes
2,048
64
2,048
64
2,112 bytes
2,048
64
2,048
64
2,048 blocks
per plane
4,096 blocks
per die
1 block
1 block
1 block
1 block
Plane 0: even-
numbered blocks
(0, 2, 4, 6, ...,
4,092, 4,094)¹
Plane 1: odd-
numbered blocks
(1, 3, 5, 7, ...,
4,093, 4,095)
Plane 0: even-
numbered blocks
(4,096, 4,098, ...,
8,188, 8,190)
Plane 1: odd-
numbered blocks
(4,097,4,099, ...,
8,189, 8,191)
I/O7
I/O0
1 page = (2K + 64 bytes)
1 block = (2K + 64) bytes x 64 pages
= (128K + 4K) bytes
1 plane = (128K + 4K) bytes x 2,048 blocks
= 2,112Mb
1 die = 2,112Mb x 2 planes
= 4,224Mb
1 device = 4,224Mb x 2 die
= 8,448Mb
Table 4:
Cycle
First
Second
Third
Fourth
Fifth
Notes:
1. Die 0, Plane 0: BA18 = 0; BA6 = 0.
Die 0, Plane 1: BA18 = 0; BA6 = 1.
Die 1, Plane 0: BA18 = 1; BA6 = 0.
Die 1, Plane 1: BA18 = 1; BA6 = 1.
2. For the 16Gb MT29F16G08FAA, the 8Gb array organization shown here applies to each chip
enable (CE# and CE2#).
Array Addressing: MT28F8G08BAA and MT29F16G08FAA
I/O7
CA7
LOW
BA7
BA15
LOW
I/O6
CA6
LOW
BA6
BA14
LOW
I/O5
CA5
LOW
PA5
BA13
LOW
I/O4
CA4
LOW
PA4
BA12
LOW
I/O3
CA3
CA11
PA3
BA11
LOW
I/O2
CA2
CA10
PA2
BA10
BA18³
I/O1
CA1
CA9
PA1
BA9
BA17
I/O0
CA0
CA8
PA0
BA8
BA16
Notes:
1. CAx = column address; PAx = page address; BAx = block address.
2. If CA11 is 1, then CA[10:6] must be “0.”
3. Die address boundary: 0 = 0–4Gb; 1 = 4Gb–8Gb.
PDF: 09005aef81b80e13/Source: 09005aef81b80eac
4gb_nand_m40a__2.fm - Rev. B 2/07 EN
14
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