MT29F8G08DAAWCA Datasheet, PDF (11/81 Pages) Micron Technology – 4Gb, 8Gb, and 16Gb x8 NAND Flash Memory

4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
Architecture
Architecture
These devices use NAND Flash electrical and command interfaces. Data, commands,
and addresses are multiplexed onto the same pins and received by I/O control circuits.
This provides a memory device with a low pin count. The commands received at the I/O
control circuits are latched by a command register and are transferred to control logic
circuits for generating internal signals to control device operations. The addresses are
latched by an address register and sent to a row decoder or a column decoder to select a
row address or a column address, respectively.
The data are transferred to or from the NAND Flash memory array, byte by byte (x8),
through a data register and a cache register. The cache register is closest to I/O control
circuits and acts as a data buffer for the I/O data, whereas the data register is closest to
the memory array and acts as a data buffer for the NAND Flash memory array operation.
The NAND Flash memory array is programmed and read in page-based operations and
is erased in block-based operations. During normal page operations, the data and cache
registers are tied together and act as a single register. During cache operations the data
and cache registers operate independently to increase data throughput.
These devices also have a status register that reports the status of device operation.
Figure 4: NAND Flash Functional Block Diagram
VCC VSS
I/Ox
I/O
Control
Address Register
Status Register
CE#
CLE
ALE
WE#
RE#
WP#
R/B#
Command Register
Control
Logic
Column Decode
NAND Flash
Array
(2 planes)
Data Register
Cache Register
PDF: 09005aef81b80e13/Source: 09005aef81b80eac
4gb_nand_m40a__2.fm - Rev. B 2/07 EN
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