|
PC28F128M29EWHF Datasheet, PDF (1/87 Pages) Micron Technology – Parallel NOR Flash Embedded Memory | |||
|
32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Features
Parallel NOR Flash Embedded Memory
JR28F032M29EWXX; PZ28F032M29EWXX; JS28F064M29EWXX
PC28F064M29EWXX; JR28F064M29EWXX; PZ28F064M29EWXX
JS28F128M29EWXX; PC28F128M29EWXX; RC28F128M29EWXX
Features
⢠Supply voltage
â VCC = 2.7â3.6V (program, erase, read)
â VCCQ = 1.65â3.6V (I/O buffers)
⢠Asynchronous random or page read
â Page size: 8 words or 16 bytes
â Page access: 25ns
â Random access: 60ns (BGA); 70ns (TSOP)
⢠Buffer program: 256-word MAX program buffer
⢠Program time
â 0.56µs per byte (1.8 MB/s TYP when using 256-
word buffer size in buffer program without VPPH)
â 0.31µs per byte (3.2 MB/s TYP when using 256-
word buffer size in buffer program with VPPH)
⢠Memory organization
â 32Mb: 64 main blocks, 64KB each, or eight 8KB
boot blocks (top or bottom) and 63 main blocks,
64KB each
â 64Mb: 128 main blocks, 64KB each, or eight 8KB
boot blocks (top or bottom) and 127 main blocks,
64 KB each
â 128Mb: 128 main blocks, 128KB each
⢠Program/erase controller
â Embedded byte/word program algorithms
⢠Program/erase suspend and resume capability
â READ operation on any block during a PRO-
GRAM SUSPEND operation
â READ or PROGRAM operation on one block dur-
ing an ERASE SUSPEND operation on another
block
⢠BLANK CHECK operation to verify an erased block
⢠Unlock bypass, block erase, chip erase, and write to
buffer capability
â Fast buffered/batch programming
â Fast block and chip erase
⢠VPP/WP# pin protection
â VPPH voltage on VPP to accelerate programming
performance
â Protects highest/lowest block (H/L uniform) or
top/bottom two blocks (T/B boot)
⢠Software protection
â Volatile protection
â Nonvolatile protection
â Password protection
â Password access
⢠Extended memory block
â 128-word (256-byte) block for permanent secure
identification
â Program or lock implemented at the factory or by
the customer
⢠Low-power consumption: Standby mode
⢠JESD47H-compliant
â 100,000 minimum ERASE cycles per block
â Data retention: 20 years (TYP)
⢠65nm single-bit cell process technology
⢠Packages (JEDEC-standard)
â 56-pin TSOP (128Mb, 64Mb)
â 48-pin TSOP (64Mb, 32Mb)
â 64-ball FBGA (128Mb, 64Mb)
â 48-ball BGA (64Mb, 32Mb)
⢠Green packages available
â RoHS-compliant
â Halogen-free
⢠Operating temperature
â Ambient: â40°C to +85°C
PDF: 09005aef84dc44a7
m29ew_32Mb-128Mb.pdf - Rev. B 11/12 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
|
▷ |