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KSZ8795CLX Datasheet, PDF (90/132 Pages) Microchip Technology – Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/RMII Interfaces
KSZ8795CLX
TABLE 4-21: ACL INDIRECT REGISTERS FOR 14 BYTE ACL RULES (CONTINUED)
Address
Name Description
Mode
Default
Port_ACL_9
ACL Port Register 9 (0x09)
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5.
Reg. 111 (0x6F) Bits[7:0] = Offset 0x09 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
Matching Fields for Layer 2
7-0
TYPE[7:0] Ether Type
R/W
00000000
Note: Layer 2, Layer 3, and Layer 4 in matching field should be in different entries. Same layer should be in same
entry.
Port_ACL_2
ACL Port Register 2 (0x02)
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5.
Reg. 111 (0x6F) Bits[7:0] = Offset 0x02 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
Matching Fields for Layer 3
7-0
IP_ADDR IP Address
R/W
[31:24]
00000000
Port_ACL_3
ACL Port Register 3 (0x03)
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5.
Reg. 111 (0x6F) Bits[7:0] = Offset 0x03 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
Matching Fields for Layer 3
7-0
IP_ADDR IP Address
R/W
[23:16]
00000000
Port_ACL_4
ACL Port Register 4 (0x04)
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5.
Reg. 111 (0x6F) Bits[7:0] = Offset 0x04 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
Matching Fields for Layer 3 IP
7-0
IP_ADDR IP Address
R/W
[15:8]
00000000
Port_ACL_5
ACL Port Register 5 (0x05)
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5.
Reg. 111 (0x6F) Bits[7:0] = Offset 0x05 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
Matching Fields for Layer 3
7-0
IP_ADDR IP Address
R/W
[7:0]
00000000
Port_ACL_6
ACL Port Register 6 (0x06)
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5.
Reg. 111 (0x6F) Bits[7:0] = Offset 0x06 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
Matching Fields for Layer 3
7-0
IP_Mask IP Mask
R/W
[31:24]
00000000
DS00002112A-page 90
 2016 Microchip Technology Inc.