KSZ8795CLX Datasheet, PDF (34/132 Pages) Microchip Technology – Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/RMII Interfaces

KSZ8795CLX
3.6.1.2 802.1p-Based Priority
For 802.1p-based priority, the KSZ8795CLX examines the ingress (incoming) packets to determine whether they are
tagged. If tagged, the 3-bit priority field in the VLAN tag is retrieved and compared against the “priority mapping” value,
as specified by the Registers 128 and 129, both Register 128 and 129 can map 3-bit priority field of 0-7 value to 2-bit
result of 0-3 priority levels. The “priority mapping” value is programmable.
Figure 3-9 illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag.
FIGURE 3-9:
802.1P PRIORITY FIELD FORMAT
The 802.1p-based priority is enabled by Bit[5] of the Port Control 0 Registers for ports 1, 2, 3, 4 and 5, respectively.
The KSZ8795CLX provides the option to insert or remove the priority tagged frame's header at each individual egress
port. This header, consisting of the two-byte VLAN Protocol ID (VPID) and the two-byte tag control information field
(TCI), is also referred to as the IEEE 802.1Q VLAN tag.
Tag insertion is enabled by bit[2] of the Port Control 0 Registers and the Port Control 8 Registers to select which source
port (ingress port) PVID can be inserted on the egress port for ports 1, 2, 3, 4 and 5, respectively. At the egress port,
untagged packets are tagged with the ingress port’s default tag. The default tags are programmed in the port control 3
and control 4 Registers for ports 1, 2, 3, 4 and 5, respectively. The KSZ8795CLX will not add tags to already tagged
packets.
Tag removal is enabled by Bit[1] of the Port Control 0 Registers for Ports 1, 2, 3, 4 and 5, respectively. At the egress
port, tagged packets will have their 802.1Q VLAN tags removed. The KSZ8795CLX will not modify untagged packets.
The CRC is recalculated for both tag insertion and tag removal.
802.1p priority field re-mapping is a QoS feature that allows the KSZ8795CLX to set the “User Priority Ceiling” at any
ingress port by the Port Control 2 Register Bit[7]. If the ingress packet’s priority field has a higher priority value than the
default tag’s priority field of the ingress port, the packet’s priority field is replaced with the default tag’s priority field.
3.6.1.3 DiffServ-Based Priority
DiffServ-based priority uses the ToS registers (Registers 144 to 159) in the “Advanced Control Registers” sub-section.
The ToS priority control registers implement a fully decoded, 128-bit differentiated services code point (DSCP) register
to determine packet priority from the 6-bit ToS field in the IP header. When the most significant six bits of the ToS field
are fully decoded, 64 code points for DSCP result. These are compared with the corresponding bits in the DSCP register
to determine priority.
3.6.2 SPANNING TREE SUPPORT
Port 5 is the designated port for spanning tree support.
The other ports (Port 1 - Port 4) can be configured in one of the five spanning tree states via the “transmit enable,”
“receive enable,” and “learning disable” register settings in Registers 18, 34, 50, and 66 for Ports 1, 2, 3, and 4, respec-
tively. The following description shows the port setting and software actions taken for each of the five spanning tree
states.
DS00002112A-page 34
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