KSZ8795CLX Datasheet, PDF (36/132 Pages) Microchip Technology – Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/RMII Interfaces

KSZ8795CLX
3.6.3 RAPID SPANNING TREE SUPPORT
There are three operational states of the discarding, learning, and forwarding assigned to each port for RSTP. Discard-
ing ports do not participate in the active topology and do not learn MAC addresses. Ports in the learning states learn
MAC addresses, but do not forward user traffic. Ports in the forwarding states fully participate in both data forwarding
and MAC learning. RSTP uses only one type of BPDU called RSTP BPDUs. They are similar to STP configuration
BPDUs with the exception of a type field set to “version 2” for RSTP and “version 0” for STP, and flag field carrying addi-
tional information.
TABLE 3-14: PORT SETTING AND SOFTWARE ACTIONS FOR RAPID SPANNING TREE
Disable State
Port Setting
Software Action
The state includes
three states of the
disable, blocking and
listening of STP.
"Transmit enable = 0,
Receive enable = 0,
Learning disable = 1."
The processor should not send any packets to the port. The switch
may still send specific packets to the processor (packets that match
some entries in the static table with “overriding bit” set) and the pro-
cessor should discard those packets. When disable the port’s learning
capability (learning disable = ’1’), set the Register 1 Bit[5] and Bit[4]
will flush rapidly with the port-related entries in the dynamic MAC
table and static MAC table. Note: processor is connected to Port 5 via
MII interface. Address learning is disabled on the port in this state.
Learning State
Only packets to and
from the processor
are forwarded.
Learning is enabled.
Port Setting
“Transmit enable = 0,
Receive enable = 0,
Learning disable = 0.”
Software Action
The processor should program the static MAC table with the entries
that it needs to receive (e.g., BPDU packets). The “overriding” bit
should be set so that the switch will forward those specific packets to
the processor. The processor may send packets to the port(s) in this
state (see “Tail Tagging Mode” section for details). Address learning is
enabled on the Port in this state.
Forwarding State
Packets are for-
warded and received
normally. Learning is
enabled.
Port Setting
“Transmit enable = 1,
Receive enable = 1,
Learning disable = 0.”
Software Action
The processor should program the static MAC table with the entries
that it needs to receive (e.g., BPDU packets). The “overriding” bit
should be set so that the switch will forward those specific packets to
the processor. The processor may send packets to the port(s) in this
state (see “Tail Tagging Mode” section for details). Address learning is
enabled on the port in this state.
3.6.4 TAIL TAGGING MODE
The tail tag is only seen and used by the Port 5 interface, which should be connected to a processor by the SW5-GMII,
RGMII, MII, or RMII interfaces. One byte tail tagging is used to indicate the source/destination port on Port 5. Only bits
[3:0] are used for the destination in the tail tagging byte. Other bits are not used. The tail tag feature is enabled by setting
Register 12 Bit[1].
FIGURE 3-10:
TAIL TAG FRAME FORMAT
DS00002112A-page 36
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