KSZ8795CLX Datasheet, PDF (102/132 Pages) Microchip Technology – Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/RMII Interfaces

KSZ8795CLX
TABLE 4-25: EEE PORT REGISTERS (CONTINUED)
Address
Name Description
Mode
Default
EEE Port Register 3
Link Partner EEE Capability Status and Local Device EEE Capability Advisement Register
Reg. 110 (0x6E) Bits[7:5] = 001 for EEE, Reg. 110 Bits[3:0] = 0xn, n = 1-4 for the Indirect Port Register,
Reg. 111 (0x6F) Bits[7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x28 (Bits[15:8]), 0x29 (Bits[7:0])
Location: (001 EEE) -> {0xn, offset} -> 0xA0 holds the data.
15
Reserved —
RO
0
14
LP
1 = EEE is supported for 10GBASE-KR
RO
0
10GBASE- 0 = EEE is not supported for 10GBASE-KR
KR EEE
Note: LP = Link Partner
13
LP
1 = EEE is supported for 10GBASE-KX4
RO
0
10GBASE- 0 = EEE is not supported for 10GBASE-KX4
KX4 EEE
12
LP
1 = EEE is supported for 1000BASE-KX
RO
0
1000BASE- 0 = EEE is not supported for 1000BASE-KX
KX EEE
11
LP
1 = EEE is supported for 10GBASE-T
RO
0
10GBASE-T 0 = EEE is not supported for 10GBASE-T
EEE
10
LP
1 = EEE is supported for 1000BASE-T
RO
0
1000BASE-T 0 = EEE is not supported for 1000BASE-T
EEE
9
LP
1 = EEE is supported for 100BASE-TX
RO
0
100BASE-TX 0 = EEE is not supported for 100BASE-TX
EEE
8-2
Reserved —
RO
7h’0
1
Local
1 = EEE is supported for 100BASE-TX
R/W
1
100BASE-TX 0 = EEE is not supported for 100BASE-TX
EEE
Note: This is for local port to support EEE capability
0
Reserved —
RO
0
EEE Port Register 4
Port EEE Wake Up Error Count Register
Reg. 110 (0x6E) Bits[7:5] = 001 for EEE, Reg. 110 Bits[3:0] = 0xn, n = 1-4 for the Indirect Port Register,
Reg. 111 (0x6F) Bits[7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x2A (Bits[15:8]), 0x2B (Bits[7:0])
Location: (001 EEE) -> {0xn, offset} -> 0xA0 holds the data.
15 - 0 EEE Wakeup This count is incremented by one whenever a
RO
Error
wakeup from LPI to Idle state is longer than the
Counter Wake-Up error threshold time specified in EEE
Global Register 4. The default of Wake-Up error
threshold time is 20.5 µs. This register is read-
cleared.
0x0000
DS00002112A-page 102
 2016 Microchip Technology Inc.