TC500 Datasheet, PDF (9/28 Pages) TelCom Semiconductor, Inc – PRECISION ANALOG FRONT ENDS

TC500/A/510/514
FIGURE 4-1:
T_TIME
Converter Status
IVnoteltgargaetorV_INT0
TYPICAL DUAL SLOPE A/D CONVERTER SYSTEM TIMING
Auto-Zero
Integrate
Full Scale Input
Reference Overshoot Integrator
De-integrate
Output
Zero
Comparator Delay
Comparator
Output
Undefined
0 For Negative Input
1 For Postive Input
A
AB Inputs
B
A=0
B=1
A=1
B=0
A=1
B=1
A=0
B=0
Controller
Operation
Begin Conversion with
Auto-Zero Phase
Time Input
Integration
Phase
Sample Input Polarity
Capture
De-integration
Time
Integrator Ready for Next
Output Conversion
Zero Phase (Auto-Zero is
Complete Idle State)
Typically = T_INT
(Positive Input Shown)
T_INT
Notes: The length of this phase is chosen almost arbitrarily
but needs to be long enough to null out worst case errors
(see text).
Comparator Delay +
Processor Latency
Minimizing
Overshoot
will Minimize
I.O.Z. Time
© 2002 Microchip Technology Inc.
DS21428B-page 9