TC500 Datasheet, PDF (6/28 Pages) TelCom Semiconductor, Inc – PRECISION ANALOG FRONT ENDS

TC500/A/510/514
3.0 DETAILED DESCRIPTION
3.1 Dual Slope Conversion Principles
Actual data conversion is accomplished in two phases:
input signal Integration and reference voltage
De-integration.
The integrator output is initialized to 0V prior to the start
of Integration. During Integration, analog switch S1
connects V_IN to the integrator input where it is main-
tained for a fixed time period (T_INT). The application of
V_IN causes the integrator output to depart 0V at a rate
determined by the magnitude of V_IN and a direction
determined by the polarity of V_IN. The De-integration
phase is initiated immediately at the expiration of T_INT.
During De-integration, S1 connects a reference voltage
(having a polarity opposite that of V_IN) to the integrator
input. At the same time, an external precision timer is
started. The De-integration phase is maintained until
the comparator output changes state, indicating the
integrator has returned to its starting point of 0V. When
this occurs, the precision timer is stopped. The De-inte-
gration time period (T_DEINT), as measured by the preci-
sion timer, is directly proportional to the magnitude of
the applied input voltage (see Figure 3-3).
A simple mathematical equation relates the Input Sig-
nal, Reference Voltage and Integration time:
EQUATION 3-1:
1
R_INTC_INT
∫ ^TINT V_IN(T)DT =
0
V_REFT_DEINT
R_INTC_INT
Where:
V_REF = Reference Voltage
T_INT = Signal Integration time (fixed)
t_DEINT = Reference Voltage Integration time (variable)
For a constant V_IN:
EQUATION 3-2:
V_IN = V_REF
T_DEINT
T_INT
The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values as long as
they are stable during a measurement cycle.
An inherent benefit is noise immunity. Input noise
spikes are integrated (averaged to zero) during the
integration periods. Integrating ADCs are immune to
the large conversion errors that plague successive
approximation converters in high noise environments.
Integrating converters provide inherent noise rejection
with at least a 20dB/decade attenuation rate. Interfer-
ence signals with frequencies at integral multiples of
DS21428B-page 6
the integration period are, theoretically, completely
removed, since the average value of a sine wave of
frequency (1/T) averaged over a period (T) is zero.
Integrating converters often establish the integration
period to reject 50/60Hz line frequency interference
signals. The ability to reject such signals is shown by a
normal mode rejection plot (Figure 3-1). Normal mode
rejection is limited in practice to 50 to 65dB, since the
line frequency can deviate by a few tenths of a percent
(Figure 3-2).
FIGURE 3-1:
INTEGRATING
CONVERTER NORMAL
MODE REJECTION
30
T = Measurment
Period
20
10
0
0.1/T
1/T
Input Frequency
10/T
FIGURE 3-2:
80
LINE FREQUENCY
DEVIATION
70
t = 0.1 sec
60
50
40
30
Normal Mode = 20 LOG
REJECTION
SIN 60 p t (1 ± ^D1E00V)
60 p t (1 ± ^D1E00V)
DEV = Deviation from 60Hz
t = Integration Period
20
0.01
0.1
1.0
Line Frequency Deviation from 60 Hz (%)
© 2002 Microchip Technology Inc.