TC500 Datasheet, PDF(13/28 Page) TelCom Semiconductor, Inc

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TC500 Datasheet, PDF (13/28 Pages) TelCom Semiconductor, Inc – PRECISION ANALOG FRONT ENDS

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FIGURE 7-1:

NOISE THRESHOLD

30 ÂµV

TC500/A/510/514

NTH

LowREF

NTH

Normal VREF

NTH

High VREF

Slope

(S)

VREF

RINT CINT

NTH

Noise

Threshold

7.6 Integrator Output Zero Phase

The comparator delay and the controller's response

latency may result in overshoot, causing charge

buildup on the integrator at the end of a conversion.

This charge must be removed or performance will

degrade. The Integrator Output Zero phase should be

activated (AB = 00) until CMPTR goes high. It is abso-

lutely critical that this phase be terminated immediately

so that Overshoot is not allowed to occur in the oppo-

site direction. At this point, it can be assured that the

integrator is near zero. Auto Zero should be entered

(AB = 01) and the TC5XX held in this state until the next

cycle is begun (see Figure 7-2).

FIGURE 7-2:

OVERSHOOT

Integrator

Output

Zero

Crossing

Comparator

Output Comp

Integrate

Phase

Overshoot

De-integrate Phase

Integrator

Zero Phase

7.7 Using the TC510/TC514

7.7.1

NEGATIVE SUPPLY VOLTAGE

CONVERTER (TC510, TC514)

A capacitive charge pump is employed to invert the volt-

age on VDD for negative bias within the TC510/TC514.

This voltage is also available on the VOUT- pin to provide

negative bias elsewhere in the system. Two external

capacitors are required to perform the conversion.

Timing is generated by an internal state machine driven

from an on-board oscillator. During the first phase,

capacitor CF is switched across the power supply and

charged to VS+. This charge is transferred to capacitor

COUT- during the second phase. The oscillator normally

runs at 100kHz to ensure minimum output ripple. This

frequency can be reduced by placing a capacitor from

OSC to VDD. The relationship between the capacitor

value is shown in Section 9.0.

7.7.2

ANALOG INPUT MULTIPLEXER

(TC514)

The TC514 is equipped with a four input differential

analog multiplexer. Input channels are selected using

select inputs (A1, A0). These are high-true control sig-

nals (i.e., channel 0 is selected when (A1, A0 = 00).

DS21428B-page 13

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