KSZ8765CLX Datasheet, PDF (88/131 Pages) Microchip Technology – Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/RMII Interfaces

KSZ8765CLX
TABLE 4-21: ACL INDIRECT REGISTERS FOR 14 BYTE ACL RULES (CONTINUED)
Address
Name Description
Mode
Default
3-2
ENB[1:0] ENABLE
R/W
00
When MD=01:
00 = The 11 bits from PM, P, REP, MM in action
field specify a count value for packets matching
MAC Address and TYPE in matching field.
The count unit is defined in FORWARD field Bit[4];
Bit[4] = 0, µs will be used.
Bit[4] = 1, ms will apply.
The FORWARDED field Bit[3] determines the algo-
rithm used to generate interrupt when counter ter-
minated. Bit[3] = 0, an 11-bit counter will be loaded
with the count value from the list and start counting
down every unit time. An interrupt will be generated
when expires, i.e., next qualified packet has not
been received within the period specified by the
value.
Bit[3] = 1, the counter is incremented every
matched packet received and the interrupt is gen-
erated while terminal count reached, the count
resets thereafter.
01 = MAC address bit field is participating in test.
10 = MAC TYPE bit field is used for test.
11 = Both MAC address and TYPE are tested
against these bit fields in the list.
When MD=10:
00 = Reserved.
01 = IP address and mask or IP protocol is enabled
to be tested accordingly.
10 = SA and DA are compared; the drop/forward
decision is based on the E/Q bit setting.
11 = Reserved
When MD=11:
00 = Protocol comparison is enabled.
01 = TCP/UDP address comparison is selected.
10 = It is same with ‘01’
11 = The sequence number of TCP is compared.
1
S_D
Source/Destination Address
R/W
0 = DA is used to compare.
1 = SA is used to compare
0
EQ
Compare Equal
R/W
0 = Match if they are not equal.
1 = Match if they are equal.
Port_ACL_2
ACL Port Register 2 (0x02)
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5.
Reg. 111 (0x6F) Bits[7:0] = Offset 0x02 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
Matching Fields for Layer 2
7-0
MAC_ADDR MAC Address
R/W
[47:40]
0
0
00000000
DS00002130A-page 88
 2016 Microchip Technology Inc.