KSZ8765CLX Datasheet, PDF (115/131 Pages) Microchip Technology – Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/RMII Interfaces

KSZ8765CLX
FIGURE 7-2:
RGMII V2.0 SPECIFICATION
TXC (SOURCE OF DATA)
TXD[8:5][3:0]
TXD[7:4][3:0]
TX_CTL
TXC (AT RECEIVER)
TXD[3:0]
TXD[8:5]
TXD[7:4]
TsetupT
TXD[4]
TXEN
TXD[9
TXERR
TsetupR
TXC (WITH INTERNAL
DELAY ADDED)
TholdT
TholdR
RXC (SOURCE OF DATA)
RXD[8:5][3:0]
RXD[7:4][3:0]
RX_CTL
RXC (AT RECEIVER)
RXD[3:0]
RXD[4]
RXDV
RXD[8:5]
RXD[7:4]
RXD[9
RXERR
TsetupT
TsetupR
RXC (WITH INTERNAL
DELAY ADDED)
TholdT
TholdR
TABLE 7-2: RGMII TIMING PARAMETERS
Symbol
Parameter
Min. Typ. Max. Units
TskewT
Data to clock output skew (at transmitter) (Note 7-1)
–500
0
500
ps
TskewR
Data to clock input skew (at receiver) (Note 7-1)
1
—
2.6
TsetupT
Data to clock output setup (at transmitter – integrated delay) 1.0
2.0
—
TholdT
TsetupR
Clock to data output hold (at transmitter – integrated delay) 1.0
2.0
—
Data to clock input setup (at receiver – integrated delay)
0.8
2.0
—
ns
TholdR
Clock to data input hold (at receiver – integrated delay)
0.8
2.0
—
Tcyc
Clock Cycle Duration (Note 7-2)
7.2
8.0
8.8
Duty_G
Duty_T
Duty Cycle for Gigabit
Duty Cycle for 10/100T
45
40
50
50
55
60
%
t_r/t_f
Note 7-1
Rise/Fall Time (20-80%)
—
—
0.75
ns
RGMII v2.0 add Internal Delay (RGMII-ID) option to match the data to clock output/input skew for
RGMII transmit and receiving, see the register 86 bits[4:3] for detail.
Note 7-2 For 10 Mbps and 100 Mbps. Tcyc will scale to 400 ns ±40 ns and 40 ns ±4 ns.
DS00002130A-page 116
 2016 Microchip Technology Inc.