KSZ8765CLX Datasheet, PDF (49/131 Pages) Microchip Technology – Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/RMII Interfaces

KSZ8765CLX
TABLE 4-3: GLOBAL REGISTERS (CONTINUED)
Address
Name
Description
4
Flush Static MAC Table Flush the matched entries in static MAC table for
RSTP
1 = Trigger the flush static MAC table operation.
0 = Normal operation.
Note: The matched entry is defined as the entry in
the Forwarding ports field contains a single port
and MAC address with unicast. This port, in turn,
has its learning capability being turned off (learning
disable). Per port, multiple entries can be qualified
as matched entries.
3
Reserved
N/A Don’t change
2
Reserved
N/A Don’t change
1
UNH Mode
1 = The switch will drop packets with 0x8808 in the
T/L filed, or DA = 01-80-C2-00-00-01.
0 = The switch will drop packets qualified as “flow
control” packets.
0
Link Change Age 1 = Link change from “link” to “no link” will cause
fast aging (<800 µs) to age address table faster.
After an age cycle is complete, the age logic will
return to normal (300 ±75 seconds).
Register 3 (0x03): Global Control 1
7
Reserved
6
2 KB Packet Support
5
IEEE 802.3x Transmit
Flow Control Disable
4
IEEE 802.3x Receive
Flow Control Disable
Note: If any port is unplugged, all addresses will be
automatically aged out.
N/A Don’t change.
1 = Enable 2 KB packet support.
0 = Disable 2 KB packet support.
0 = Enables transmit flow control based on AN
result.
1 = Will not enable transmit flow control regardless
of the AN result.
0 = Enables receive flow control based on AN
result.
1 = Will not enable receive flow control regardless
of the AN result.
Note: Bit[5] and Bit[4] default values are controlled
by the same pin, but they can be programmed
independently.
3
Frame Length Field 1 = Check frame length field in the IEEE packets. If
Check
the actual length does not match, the packet will be
dropped (for L/T <1500).
2
Aging Enable
1 = Enable aging function in the chip.
0 = Disable aging function.
1
Fast-Age Enable
1 = Turn on fast aging (800 µs).
0
Aggressive Back-Off 1 = Enable more aggressive back-off algorithm in
Enable
half duplex mode to enhance performance. This is
not in the IEEE standard.
Mode
R/W
(SC)
RO
RO
R/W
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
1
1
0
0
0
0
0
0
0
1
0
0
 2016 Microchip Technology Inc.
DS00002130A-page 49