PIC24FV32KA304-I Datasheet, PDF (84/320 Pages) Microchip Technology – 20/28/44/48-Pin, General Purpose, 16-Bit Flash Microcontrollers with XLP Technology

PIC24FV32KA304 FAMILY
REGISTER 8-2: CORCON: CPU CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
R/C-0, HSC
R/W-0
U-0
U-0
—
—
—
—
IPL3⁽²⁾
PSV⁽¹⁾
—
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-4
bit 3
bit 1-0
Unimplemented: Read as ‘0’
IPL3: CPU Interrupt Priority Level Status bit⁽²⁾
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
Unimplemented: Read as ‘0’
Note 1: See Register 3-2 for the description of this bit, which is not dedicated to interrupt control functions.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
Note: Bit 2 is described in Section 3.0 “CPU”.
DS39995B-page 84
 2011 Microchip Technology Inc.