PIC24FV32KA304-I Datasheet, PDF (142/320 Pages) Microchip Technology – 20/28/44/48-Pin, General Purpose, 16-Bit Flash Microcontrollers with XLP Technology

PIC24FV32KA304 FAMILY
11.2.2 I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically, this instruction
would be a NOP.
11.3 Input Change Notification
The input change notification function of the I/O ports
allows the PIC24FV32KA304 family of devices to
generate interrupt requests to the processor in
response to a Change-of-State (COS) on selected
input pins. This feature is capable of detecting input
change of states, even in Sleep mode, when the clocks
are disabled. Depending on the device pin count, there
are up to 23 external signals (CN0 through CN22) that
may be selected (enabled) for generating an interrupt
request on a Change-of-State.
There are six control registers associated with the CN
module. The CNEN1 and CNEN2 registers contain the
interrupt enable control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
Each CN pin also has a weak pull-up/pull-down
connected to it. The pull-ups act as a current source
that is connected to the pin. The pull-downs act as a
current sink to eliminate the need for external resistors
when push button or keypad devices are connected.
On any pin, only the pull-up resistor or the pull-down
resistor should be enabled, but not both of them. If the
push button or the keypad is connected to VDD, enable
the pull-down, or if they are connected to VSS, enable
the pull-up resistors. The pull-ups are enabled
separately using the CNPU1 and CNPU2 registers,
which contain the control bits for each of the CN pins.
Setting any of the control bits enables the weak
pull-ups for the corresponding pins. The pull-downs are
enabled separately, using the CNPD1 and CNPD2
registers, which contain the control bits for each of the
CN pins. Setting any of the control bits enables the
weak pull-downs for the corresponding pins.
When the internal pull-up is selected, the pin uses VDD
as the pull-up source voltage. When the internal
pull-down is selected, the pins are pulled down to VSS
by an internal resistor. Make sure that there is no
external pull-up source/pull-down sink when the
internal pull-ups/pull-downs are enabled.
Note:
Pull-ups and pull-downs on change notifi-
cation pins should always be disabled
whenever the port pin is configured as a
digital output.
EXAMPLE 11-1: PORT WRITE/READ EXAMPLE
MOV
MOV
NOP;
BTSS
0xFF00, W0;
W0, TRISB;
PORTB, #13;
//Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs
//Delay 1 cycle
//Next Instruction
Equivalent ‘C’ Code
TRISB = 0xFF00;
NOP();
if(PORTBbits.RB13 == 1)
{
}
//Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs
//Delay 1 cycle
// execute following code if PORTB pin 13 is set.
DS39995B-page 142
 2011 Microchip Technology Inc.