24LC22A-I Datasheet, PDF (8/24 Pages) Microchip Technology – 2K VESA E-EDID Serial EEPROM

24LC22A
FIGURE 3-5:
BUS TIMING START/STOP
SCL
SDA
TSU:STA
THD:STA
VHYS
TSU:STO
Start
Stop
FIGURE 3-6:
BUS TIMING DATA
TF
SCL
TSU:STA
SDA
IN
TSP
TAA
TLOW
THD:STA
THIGH
THD:DAT
TAA
SDA
OUT
TR
TSU:DAT _TSU:STO
TBUF
3.1.6 SLAVE ADDRESS
After generating a Start condition, the bus master trans-
mits the slave address consisting of a 7-bit device code
(1010000) for the 24LC22A.
The eighth bit of slave address determines whether the
master device wants to read or write to the 24LC22A
(Figure 3-7).
The 24LC22A monitors the bus for its corresponding
slave address continuously. It generates an
Acknowledge bit if the slave address was true and it is
not in a programming mode.
Operation
Slave Address
R/W
Read
1010000
1
Write
1010000
0
FIGURE 3-7:
Start
CONTROL BYTE
ALLOCATION
Read/Write
Slave Address
R/W A
1
0
1
0
0
0
0
DS21683B-page 8
© 2007 Microchip Technology Inc.