24LC22A-I Datasheet, PDF (3/24 Pages) Microchip Technology – 2K VESA E-EDID Serial EEPROM

24LC22A
1.2 AC Characteristics
AC CHARACTERISTICS
Vcc = +2.5V to 5.5V
Industrial (I):
TAMB = -40°C to +85°C
Param.
No.
Sym.
Parameter
Min.
Max.
Units
Conditions
1
FCLK Clock frequency
2
THIGH Clock high time
—
—
4000
600
100
kHz 2.5V ≤ VCC ≤ 5.5V
400
4.5V ≤ VCC ≤ 5.5V
—
ns 2.5V ≤ VCC ≤ 5.5V
—
4.5V ≤ VCC ≤ 5.5V
3
TLOW Clock low time
4700
1300
—
ns 2.5V ≤ VCC ≤ 5.5V
—
4.5V ≤ VCC ≤ 5.5V
4
TR SDA and SCL rise time
—
1000
ns 2.5V ≤ VCC ≤ 5.5V (Note 1)
—
300
4.5V ≤ VCC ≤ 5.5V (Note 1)
5
TF SDA and SCL fall time
—
300
ns (Note 1)
—
300
6
THD:STA Start condition hold time
4000
600
—
ns 2.5V ≤ VCC ≤ 5.5V
—
4.5V ≤ VCC ≤ 5.5V
7
TSU:STA Start condition setup time
4700
600
—
ns 2.5V ≤ VCC ≤ 5.5V
—
4.5V ≤ VCC ≤ 5.5V
8
THD:DAT Data input hold time
0
—
ns (Note 2)
0
—
9
TSU:DAT Data input setup time
250
—
ns 2.5V ≤ VCC ≤ 5.5V
100
—
4.5V ≤ VCC ≤ 5.5V
10
TSU:STO Stop condition setup time
11
TAA Output valid from clock
(Note 2)
4000
600
—
—
—
—
3500
900
ns 2.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
ns 2.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
12
TBUF Bus free time: Time the bus must be
4700
free before a new transmission can
1300
start
—
ns 2.5V ≤ VCC ≤ 5.5V
—
4.5V ≤ VCC ≤ 5.5V
13
TOF Output fall time from VIH
minimum to VIL maximum
—
250
20+0.1CB
250
ns 2.5V ≤ VCC ≤ 5.5V (Note 1)
4.5V ≤ VCC ≤ 5.5V (Note 1)
14
TSP Input filter spike suppression
(SDA and SCL pins)
—
50
ns (Notes 1 and 3)
—
50
15
TWR Write cycle time (byte or page)
—
10
ms
—
10
16
TVAA Output valid from VCLK
—
2000
ns
—
1000
17
TVHIGH VCLK high time
4000
—
ns
600
—
18
TVLOW VCLK low time
4700
—
ns
1300
—
19
TVHST VCLK setup time
0
—
ns
0
—
20
TSPVL VCLK hold time
4000
—
ns
600
—
21
TVHZ Mode transition time
—
1000
ns
—
500
22
TVPU Transmit-Only power up time
0
—
ns
0
—
23
TSPV Input filter spike suppression (VCLK
—
pin)
—
100
ns
100
24
—
Endurance
1M
—
cycles 25°C, VCC = 5.0V, Block mode
(Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of
the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to Schmitt Trigger inputs which provide improved noise spike suppression.
This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but established by characterization. For endurance estimates in a specific application, please
consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
© 2007 Microchip Technology Inc.
DS21683B-page 3