24LC22A-I Datasheet, PDF (6/24 Pages) Microchip Technology – 2K VESA E-EDID Serial EEPROM

24LC22A
FIGURE 3-3:
DISPLAY OPERATION PER DDC STANDARD PROPOSED BY VESA^®
Display Power-on
or
DDC Circuit Powered
from +5 volts
Communication
is idle
Is Vsync
No
present?
Yes
Send EDID continuously
using Vsync as clock
High-to-Low
No
transition on
SCL?
Yes
Stop sending EDID.
Switch to DDC2™ mode.
High-to-Low
transition on
No
SCL?
Yes
DDC2 communication
idle. Display waiting for
address byte.
No
No
Display has
optional
transition state
?
Yes
Set Vsync counter = 0
or start timer
No
DDC2B
address
received?
Reset counter or timer
No
Change on
SCL, SDA or
VCLK lines?
Yes
High-low
transition on SCL
?
Yes
Reset Vsync counter = 0
Is display
Access.busTM
capable?
Yes
Valid Access.bus
address?
Yes
Receive DDC2B
command
Respond to DDC2B
command
No
No
Valid
Yes
DDC2 address
received?
No
No
VCLK
cycle?
Yes
Increment VCLK counter
(if appropriate)
No
Counter=128 or
timer expired?
Yes
Switch back to DDC1™
mode.
Yes
See Access.bus
specification to determine
correct procedure.
The 24LC22A was designed to
comply to the portion of flowchart inside dash box.
Note 1: The base flowchart is copyright © 1993, 1994, 1995 Video Electronic Standard Association (VESA) from
VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA.
2: The dash box and text “The 24LC21A and... inside dash box.” are added by Microchip Technology Inc.
3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LCS22A.
DS21683B-page 6
© 2007 Microchip Technology Inc.